EE 360N - Programming Assignment 6 Clarifications

  1. Clarification on the values of the control signals. We will check the values of the internal pipeline latches generated by your simulator, so make sure you follow these conventions.

  2. If the D-Cache is not enabled (V.DCACHE.EN signal is 0), the data output by the D-Cache should be set to 0x0000.

  3. Control store entries corresponding to invalid opcodes (opcodes 1010 and 1011) should be set to all 0.

  4. Will you check the values in pipeline latches even if the latches are invalid?

    If the pipeline latches in a stage are invalid, our grading script is still going to check the values in the latch. The datapath of a stage performs calculations regardless of whether or not the instruction in that stage is valid (unless the valid bit is explicitly input to some logic blocks to gate the calculations). For example, even if AGEX.V is 0, the address generation logic, shifter, and the ALU will still perform calculations based on the data values in AGEX latches and control signals in AGEX.CS latch. At the end of the cycle, calculated outputs of these units will be latched into the MEM latches. Concurrently, AGEX.V is propagated to MEM.V.

  5. If you downloaded the shell code before 10:13am on Wednesday, December 7, please change the definition of the Low16bits macro to the following:
         #define Low16bits(x) ((x) & 0xFFFF)
    This change makes sure that the correct order of operations will be followed for the macro.

  6. Since we have not provided a standard data set to use with your even8 program, you are NOT required to submit the dumpsim file. However, you should make sure that your implementation works correctly before submitting!