If the pipeline latches in a stage are invalid, our grading script is still going to check the values in the latch. The datapath of a stage performs calculations regardless of whether or not the instruction in that stage is valid (unless the valid bit is explicitly input to some logic blocks to gate the calculations). For example, even if AGEX.V is 0, the address generation logic, shifter, and the ALU will still perform calculations based on the data values in AGEX latches and control signals in AGEX.CS latch. At the end of the cycle, calculated outputs of these units will be latched into the MEM latches. Concurrently, AGEX.V is propagated to MEM.V.
#define Low16bits(x) ((x) & 0xFFFF)This change makes sure that the correct order of operations will be followed for the macro.