F: Fetch stage D: Decode stage A: AGEX stage M: Memory stage S: SR stage Cycle Instruction 1 2 3 4 5 6 7 8 9 10 ----------------------------------------------- ADD R0, R0, #0 F F D A M S ADD R1, R1, R1 F D A M S ADD R2, R3, R4 F D A M S ADD R3, R4, #10 F D A M S HALT F D A M S