- Briefly explain the difference between the microarchitecture
level and the ISA level in the transformation hierarchy. What information
does the compiler need to know about the microarchitecture of the
machine for which it's compiling code?
Classify the following attributes of LC-3b as either a property of
its microarchitecture or ISA:
- There is no subtract instruction in LC-3b.
- The ALU of LC-3b does not have a subtract unit.
- LC-3b has three condition code bits (n, z, and p).
- The n, z, and p bits are stored in three 1-bit registers.
- A 5-bit immediate can be specified in an ADD instruction
- It takes n cycles to execute an ADD instruction.
- There are 8 general purpose registers used by operate, data movement
and control instructions.
- The registers MDR and MAR are used for Loads and Stores.
- A 2-to-1 mux feeds one of the inputs to ALU.
- The register file has one input and two output ports.
- Both of the following programs cause the value
x0004 to be stored in location x3000, but they do so at different times.
Explain the difference.
AND R0, R0, #0
ADD R0, R0, #4
LEA R1, A
LDW R1, R1, #0
STW R0, R1, #0
A .FILL x3000
- Classify the LC-3b instructions into Operate,
Data Movement, or Control instructions.
- At location x3E00, we would like to put an
instruction that does nothing. Many ISAs actually have an opcode devoted
to doing nothing. It is usually called NOP, for NO OPERATION. The instruction
is fetched, decoded, and executed. The execution phase is to do nothing!
Which of the following three instructions could be used for NOP and have
the program still work correctly?
What does the ADD instruction do that the others do not do?
- 0001 001 001 1 00000
- 0000 111 000000010
- 0000 000 000000000
- Consider the following LC-3b assembly language program:
AND R5, R5, #0
AND R3, R3, #0
ADD R3, R3, #8
LEA R0, B
LDW R1, R0, #1
LDW R1, R1, #0
ADD R2, R1, #0
AGAIN ADD R2, R2, R2
ADD R3, R3, #-1
LDW R4, R0, #0
AND R1, R1, R4
NOT R1, R1
ADD R1, R1, #1
ADD R2, R2, R1
ADD R5, R5, #1
B .FILL XFF00
A .FILL X4000
- The assembler creates a symbol table after the first pass. Show
the contents of this symbol table.
- What does this program do? (in less than 25 words)
- When the programmer wrote this program, he/she did not take full
advantage of the instructions provided by the LC-3b ISA. Therefore the program
executes too many unnecessary instructions. Show what the programmer should
have done to reduce the number of instructions executed by this program.
- Consider the following LC-3b assembly language
MAIN LEA R2,L0
L0 ADD R0,R0,#5
L1 ADD R1,R1,#5
- Assemble the above program. Show the LC-3b machine code for each instruction in the program as a hexadecimal number.
- This program shows two ways to call a subroutine. One requires two instructions:
LEA, JSRR. The second requires only one instruction: JSR. Both ways work
correctly in this example. Is it ever necessary to use JSRR? If so, in what
- Consider the following possibilities for saving
the return address of a subroutine:
Which of these possibilities supports subroutine nesting, and which supports
subroutine recursion (that is, a subroutine that calls itself)?
- In a processor register.
- In a memory location associated with the subroutine. A different
memory location is used for each different subroutine.
- On a stack.
- A small section of byte-addressable memory is given below:
Add the 16-bit two's complement numbers specified by addresses 0x1000 and
- The ISA specifies a little-endian format
- The ISA specifies a big-endian format
- Say we have 32 mega bytes of storage, calculate the number of
bits required to address a location if
- The ISA is bit-addressable
- The ISA is byte-addressable
- The ISA is 128-bit addressable
- A zero-address machine is a stack-based machine where all operations
are done using values stored on the operand stack. For this problem, you
may assume that its ISA allows the following operations:
Note: To compute A - B with a stack machine, the following sequence
of operations are necessary: PUSH A, PUSH B, SUB. After execution of SUB,
A and B would no longer be on the stack, but the value A-B would be at
the top of the stack.
- PUSH M - pushes the value stored at memory location M onto
the operand stack.
- POP M - pops the operand stack and stores the value into memory
- OP - Pops two values off the operand stack, performs the binary
operation OP on the two values, and pushes the result back onto the
- A one-address machine uses an accumulator in order to perform computations.
For this problem, you may assume that its ISA allows the following operations:
- LOAD M - Loads the value stored at memory location M onto the
- STORE M - Stores the accumulator value into Memory Location
- OP M - Performs the binary operation OP on the value stored
at memory location M and the value present in the accumulator. The result
is stored back in the accumulator (ACCUM = ACCUM OP M).
- A two-address machine takes two sources, performs an operation
on these sources and stores the result back into one of the sources. For
this problem, you may assume that its ISA allows the following operation:
- OP M1, M2 - Performs a binary operation OP on the values stored
at memory locations M1 and M2 and stores the result back into memory location
M1 (M1 = M1 OP M2).
Note 1: OP can be ADD, SUB or MUL for the purposes of this problem.
Note 2: A, B, C, D, E and X refer to memory locations and can be also used to store temporary results.
- Write the assembly language code for calculating the expression (do not simplify the expression):
X = (A + (B * C)) * (D - (E + ( D * C )))
- In a zero-address machine
- In a one-address machine
- In a two-address machine
- In a three-address machine like the LC-3b, but which can do
memory to memory operations and also has a MUL instruction.
- Give an advantage and a disadvantage of a one-address machine versus a zero-address machine.
- The following table gives the format of the instructions for the LC-1b
computer that has 8 opcodes.
Interpretation of all instructions is similar to that of the LC-3b,
unless specifically stated otherwise.
The destination register for the instructions LDImm and
LEA is always register R0.
(e.g. LDImm #12 loads decimal 12 to register R0.)
TR stands for Target Register. In the case of the conditional
branch instruction BR, it contains the target address of the branch.
In the case of LD, it contains the source of the load. In the
case of ST, it contains the destination of the store.
ADD and AND provide immediate addressing by means of a steering bit,
bit, labeled A. If A is 0, the second source operand is obtained
from SR. If A is 1, the second source operand is obtained by
sign-extending bits[1:0] of the instruction. A bit is called a
Steering Bit if its value "steers" the interpretation of other bits
(instruction bits 1:0 in this case).
Bits labeled 0 must be zero in the encoding of the instruction.
- What kind of machine (n-address) does the above ISA specification
- How many general purpose registers does the machine have?
- Using the above instructions, write the assembly code to implement
a register to register mov operation.
- How can we make a PC-relative branch? (HINT: You will need more than one LC-1b instruction)
- Answer the following short questions.
- A memory's addressability is 64 bits. What does that tell you about the sizes of the MAR and the MDR?
- We want to increase the number of registers that we can specify in the LC-3b ADD instruction to 32. Do you see any problem with that? Explain.
- Please go to the handouts section of the course web site, print and fill out the student information sheet, and turn it in with a recognizable recent photo of yourself on September 14th.