12/13/2006
A student writes, Hi Dr. Patt, This is my first e-mail all semester, but I finally came up with a question that I think is worth your time. It has to do with memory mapped I/O, more specifically question #9 on problem set 6 (shown below.) I had the whole table right, except for the memory enable signal on the second memory access of the LDR instruction. Since xFE02 is in R0 shouldn't the memory enable bit be a 1 since the KBDR is in fact location xFE02 in memory? Wouldn't any "memory access" require memory to be enabled? Actually xFE02 is NOT part of memory. Memory is enabled ONLY if the address corresponds to a location in MEMORY. In this case, the Address Control Logic would the see the address xFE02, and would decide that this address does not correspond to a location in memory but rather refers to one of the device registers, in this case the KBDR. Therefore, the memory enable signal would be a 0. I guess the fact that the KBDR has no control signals going to it in the figure confused me. When I think of the device registers in the LC-3 I think of specific memory locations that correspond to them. Everything I have done with input and output is a simple operation performed on these memory locations. The device registers correspond to specific addresses, not actual memory locations. You need to know that when you load from or store to these special addresses, you are actually reading from or writing to one of the device registers, not memory. Thanks, <<name withheld>> Good luck preparing for the final exam. Veynu (subbing in for Dr. Patt)