Department of Electrical and Computer Engineering The University of Texas at Austin EE 382N, Spring 2006 Yale Patt, Instructor Danny Lynch, Chang Joo Lee, TAs Superscalar Flynn's bottleneck Balanced Design Amdahl's Law Internal Dataflow Instruction Supply Processing Unit Data Supply Condition Codes Aliasing Renaming Side effects Science of Tradeoffs One register Machine Register Spill Orthogonal Instruction Set Fixed Length Decode Variable Length Decode Delayed Branch Delay Slot Overlapping Register Windows Pentium Pro Decoder Predecode bits (in icache) VLIW EPIC Template bits Bitvector for Register Save Clock Skew Critical Path/Speed Path Von Neumann's Bottleneck Horizontal Microcode Vertical Microcode Branch Predictor Predication Multipath Hammock Static Prediction Backward Taken Forward Not Taken Last Time Predictor Two Bit Counter Two Level Predictor Pattern History Table Branch History Register Global History Shared History Per Branch History Global Table Shared Table Per Branch Table Profiling Representativeness Interference Gshare Agree Hybrid Predictor Perceptron Neural Networks Training Set Linear Function Trace Driven Simulator Cache Pollution Trace Cache Inactive Issue Branch Promotion Trace Packing Partial Matching Multi-Block icache Fill Unit Fill Latency Multiple Branch Predictor Triad Renaming Register Alias Table Reservation Station Tomasulo Algorithm Memory Disambiguation/Unknown Address Problem Path Associativity Block Structured ISA Basic Block Atomic Unit Internal Register File Faulting Branch Trapping Branch Store Buffer Reorder Buffer Precise Exceptions Superblock Hyperblock Multithreading Simultaneous Multithreading (SMT) Subordinate Simultaneous Multithreading (SSMT) Subordinate Thread/Helper Thread Fireball (2x clock)