EE 382N - Handouts and References
Spring 2006
- Papers
- Cache Coherence Papers
- Goodman: R. Goodman, "Using Cache Memory to Reduce Processor-Memory Traffic", Proceedings of the 10th Annual International Symposium on Computer Architecture, pp 124-131, 1983 [pdf]
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Illinois: Mark S. Papamarcos, Janak H. Patel "A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories", Proceedings of the 11th Annual International Symposium on Computer Architecture, pp 348-354, 1984 [pdf]
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Rudolph/Segall: Larry Rudolph, Zary Segall, "Dynamic Decentralized Cache Schemes for MIMD Parallel Processors" Proceedings of the 11th Annual International Symposium on Computer Architecture, pp 340-347, 1984 [pdf]
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Berkeley: Katz, R.H., S.J Eggers, et. al., "Implementing a Cache Consistency Protocol" The 12th Annual International Symposium on Computer Architecutre, June 1985, pp. 276-283. [pdf]
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Dragon: McCReight, E. "The Dragon computer system: An early overview", Technical Report, Xerox Corporation, Sept. 1984.
- Glenn Hinton, Dave Sager, Mike Upton, Darrell Boggs, Doug Carmean, Alan Kyker,Patrice Roussel, "The Microarchitecture of the PentiumŪ 4 Processor", Intel Technology Journal, 2001 [pdf]
- Mary D. Brown, Jared Stark, and Yale N. Patt, "Select-Free Instruction Scheduling Logic," Proceedings of the 34th ACM/IEEE International Symposium on Microarchitecture, Austin, Texas, December 2001. [pdf]
- Subbarao Palacharla, Norman P. Jouppi, J. E. Smith, "Complexity-effective superscalar processors", Proceedings of the 24th Annual International Symposium on Computer Architecture, 1997. [pdf]
- Mario Daniel Nemirovsky, Forrest Brewer, Roger C. Wood
"DISC: dynamic instruction stream computer",
Proceedings of the 24th International Symposium on Microarchitecture, 1991.
[pdf]
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Scott A. Mahlke et al, "Effective Compiler Support for Predicated Execution Using the Hyperblock", 25th Annual International Symposium on Microarchitecture, 1992. [pdf]
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W.M. Hwu et al, "The Superblock: An Effective Technique for VLIW and Superscalar Compilation," J. Supercomputing, vol. 7, no. 1, pp. 229-248, May 1993.[ pdf ]
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Eric Hao, Po-Yung Chang, Marius Evers, and Yale N. Patt, "Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures" Proceedings of the 29th ACM/IEEE International Symposium on Microarchitecture, Paris, France, November 1996.[pdf]
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Sanjay J. Patel and Steven S. Lumetta,
"rePLay : a Hardware Framework for Dynamic Program Optimization",
University of Illinois Technical Report, CRHC-99-16, December 1999.[ps]
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Sanjay J. Patel, Marius Evers, and Yale N. Patt,"Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing", Proceedings of the 25th International Symposium on Computer Architecture, Barcelona, Spain, June 1998.[ pdf ]
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Daniel H. Friendly, Sanjay J. Patel, and Yale N. Patt, "Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism", Proceedings of the 30th ACM/IEEE International Symposium on Microarchitecture, Research Triangle Park, North Carolina, November 1997.[ pdf ]
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Eric Rotenberg, Steve Bennett, Jim Smith, "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching," Proceedings of the 29th International Symposium on Microarchitecture, December 1996.[ pdf ]
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Daniel A. Jimenez, Calvin Lin, "Dynamic Branch Prediction with Perceptrons", HPCA 2000. [ pdf ]
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Marius Evers, Po-Yung Chang, and Yale N. Patt, "Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches", Proceedings, 23th International Symposium on Computer Architecture, Philadelphia, PA, May 1996.[ pdf ]
- S. McFarling, "Combining Branch Predictors," Digital Equipment Corporation - Western Research Laboratory, Tech. Rep. WRL Technical Note TN-36, 1993.[ pdf ]
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Eric Sprangle, Robert S. Chappell, Mitch Alsup, and Yale N. Patt, "The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference," Proceedings of the 24th International Symposium on Computer Architecture, Denver, June 1997.[ ps ]
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Po-Yung Chang, Eric Hao, Tse-Yu Yeh, and Yale Patt, "Branch Classification: A New Mechanism for Improving Branch Predictor Performance," Proceedings of the 27th International Symposium on Microarchitecture, San Jose, California, November 1994. [ps]
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Tse-Yu Yeh and Yale Patt, "Two-Level Adaptive Training Branch Prediction", Proceedings, 24th International Symposium and workshop on Microarchitecture, Albuquerque, November 1991.[ pdf ]
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J. Lee and A. Smith, "Branch prediction strategies and branch target buffer design" IEEE Computer Magazine, 17(1), 1984.[ pdf ]
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James E. Smith, "A Study of Branch Prediction Strategies" Proceedings of the 8th International Symposium on Computer Architecture, 1981.[ pdf ]
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John Swensen and Yale Patt, "Fast temporary storage for serial and parallel execution" Proceedings of the 14th International Symposium on Computer Architecture, June 1987.[ pdf ]
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Yale Patt, Wen-mei Hwu, and Michael Shebanow. "HPS, a new microarchitecture: rationale and introduction," Proceedings of the 18th annual workshop on Microprogramming, December 1985.[ pdf]
- Related Links
- LC-3b
- The LC-3b ISA. [pdf]
- LC-3b Appendix C [pdf]
- LC-3b pipeline design homework from fall 2005 360N lab6
- The Intel Manuals: with 64bit Extension
- IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture
- IA-32 Intel Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
- IA-32 Intel Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z
- IA-32 Intel Architecture Software Developer's Manual Volume 3A: System Programming Guide
- IA-32 Intel Architecture Software Developer's Manual Volume 3B: System Programming Guide
- The Intel Manuals : Old Version - without 64bit Extension
- spring 2004 EE382N Homeworks