Department of Electrical and Computer Engineering The University of Texas at Austin EE 382N, Spring 2006 Homework 3 Due: No Due Date Yale Patt, Instructor Danny Lynch, Chang Joo Lee, TAs Note: This assignment is for your own use in planning your term project. It does not have to be turned in. However, we strongly encourage you to start work on this early. Doing this assignment will aid you in catching problems before they become major hassles. Part 1. Augment your Data Path to handle the following : Prefixes: segment override (all), operand size. Scalar Instructions: CMOVC, JNE, JNBE, HLT, SAL, SAR, NOP, PUSH, POP. SIMD Instructions: PADDD, PADDW, PADDSW, PSLLD, PSLLW, PSRAD, PSRAW, MOVQ Addressing Modes: SIB byte. Data Types: byte, word, packed double word, packed word. Notes for SIMD instructions: -Using the operand size prefix for the SIMD instructions is reserved. -You should only implement the instructions that use the 64-bit registers (the mm registers) not the 128-bit registers (the xmm registers). Show all control signals needed to control the new (ie. augmented) data path. (In homework set 4 we shall start specifying the logic needed to produce those control signals). Part 2. Enter the additions of Part 1 above into your Verilog specification. Part 3. To test your augmented specification, select five more instructions with appropriate addressing modes and prefixes. Calculate the number of cycles required to execute each of these five instructions. Your results will depend on your choices, of course. For purposes of this assignment, assume 10 nsec cycle time, single-cycle cache access, 100 nsec memory access time, data cache hit ratio of 0.80, instruction cache hit ratio of 0.95. and no page faults.