Department of Electrical and Computer Engineering The University of Texas at Austin EE 382N, Spring 2006 Yale Patt, Instructor Danny Lynch, Chang Joo Lee, TAs Project FAQ Q. Should I use the SRAM module for the cache or can I use the RAM module? A. please use SRAM parts for main memory and use RAM parts for the cache. Q. Can TLB value be changed during simulations? A. No. TLB is only initialized at the beginning. Please expose the TLB setting into the top module so that you can set it up easily. Q. Can Push or Pop generate an exception? A. We assume that all stack space is on the memory. So stack operation does not generate an exception. (The segment override applies to the POP destination or the PUSH source. Not the stack access which always uses the SS segment.) Q. Does REP MOVS allow interrupt or exception during REP MOVS operation? A. Yes. A repeating string operation can be suspended by an exception or interrupt. When this happens, the state of the register is preserved to allow the string operation to be resumed upon a return from the exception or interrupt handler. (Manual 2 or 2B) Q. Is there a possibility of the program stream having branch hints (2E, 3E) which would otherwise be recognised as CS,DS seg override prefixes ? A. For the project, you can assume that there is no branch hint prefix. Q. How is the interrupt going to be generated for the testing of our designs? A. Interrupt is generated by one of the I/O devices. To service this interrupt, your machine should do a context switch and execute the interrupt service routine (which can read from /write to the I/O device), Upon completion of the service routine, execution should be redirected to the original program. Q. Then how the interrupt can be tested since you don't know our I/O device. A. We do not provide the program for testing interrupt. It is your job to write a test case that demonstates that your machine can handle interrupts. Q. What is the size of each entry in IDT? A. Each IDT entry has 64 bits. so GP address will be IDTR + 13 * 8 PF address will be IDTR + 14 * 8 Q. Do you provide any test programs to test our design and implementation? A. We do not provide test programs. It is part of your job to make test programs. Note that you can use the x86 assembler on the Linux machines in LRC to build your test programs. The executable name is "as86". The assembler will make your job much easier when you test your design. For more information on how to use the assembler, please type "man as86" on a Linux machine. Q. What is the maximum size of the segment? A. Segment limit is 20 bits, which means a segment can be up to 1MB. Q. Should we implement CALL ptr16:16 and far RET? A. You do not need to implement the instruction CALL ptr16:16 or the respective far return instruction (i.e. far return with an operand size override prefix). The push(CS) and pop(CS) operation in the CALL should perform the 32bit push and pop as the homework 3 FAQ says. You need to implement near CALLs and RETs on the specification. Therefore your design should support push(IP)(16bit push) and push(EIP)(32bit push) and the correspoding pops for these instructions. Q. Can memory data accesses be across the boundary of pages? A. Yes. You should support a memory access across the boundary of pages. This means that if the data you are accessing is in two different pages and the pages are all in the TLB, the processor should not generate a page fault and get the data correctly by accessing both pages. Q. How can we load intial data into the SRAM or ROM modules? A. Please use $readmemb and $readmemh for initializing the memory modules. $readmemb reads binary numbers from a text file and $readmemh reads hexadecimal numbers. The syntactic is $readmemb("data_filename", memory_module_name.mem); $readmemh("data_filename", memory_module_name.mem);