What must be done to read a value in a register?
I have computer access for a couple of hours, and found this message
waiting for me to deal with. So, I will answer this. BUT, please know
that subsequent questions may have to wait until I get back in town late
A student writes:
Dear Dr. Patt,
I wanted to clarify something regarding the data path
and state machine of the LC-3b, which also applies to Lab 3.
In State 33, for instance, MDR <- M requires that the LD.MDR
control bit be enabled so that the data "coming into" MDR gets stored.
Indeed, LD.MDR must be asserted in order for the MDR to be loaded at the END
of that cycle.
Now, in State 35, where IR <- MDR:
I know that LD.IR and GateMDR need to be enabled,
but does LD.MDR also need to be enabled again?
No. If there is a connection (16 wires in the case of a 16-bit quantity)
between A and what I am doing with the value in A, then I do not need a
LD.A signal to be asserted. That is, whatever is in A is always available
to whatever sources A. To write to A (i.e., to CHANGE the contents of A)
requiers LD.A to be asserted. If LD.A is not asserted, A remains unchanged
at the end of the cycle. Either way, A can be read throughout the cycle
and does not need any control signal to accomplish that. Of course, if you
need to source A onto the bus, you do need GateA to be asserted, but based
on your statements above, you knew that.
What I am confused about is whether the value in MDR is
available from the previous cycle even if LD.MDR is disabled
I would have said "regardless whether."
in the current cycle. If so, then
enabling GateMDR alone should be sufficient to put the MDR value
onto the BUS, correct?
I would really appreciate your help in this matter.
<<name withheld to protect ...>>