what goes on in a clock cycle
A student writes:
In the datapath, if a value is on the BUS for a particular:
for example PC<--BaseR, you gate the MARMUX onto the BUS,
After the value has been latched by the PC, is the value on the BUS
accesible, or is the BUS now empty i.e. BUS = 0.
<<name withheld to protect ...>>
Apparently this is still not clear. There are two kinds of control signals,
those that latch state information (e.g., LD.PC) and those that process
information during the cycle (e.g., ALUK, GatePC).
At the START of a clock cycle, all the control signals for that cycle become
active. Some of them (9) are used in the microsequencer to figure out what
state (and consequently what control signals) will be active in the
following clock cyle. The rest (26) are used to control the data path.
Of the 26, those that process information (combinational logic) are active
for the whole cycle. As the cycle progresses, information is propagated
through the various combinational logic. At the end of the cycle, whatever
is on the inputs of any storage device is latched depending on its load
So, getting back to the student's question:
Gate MARMUX onto the bus. What is gated onto the bus. Initially, garbage,
since the value to be gated has not yet gone through the MARMUX. As the
cycle progresses, the output of the MARMUX stablizes once the signals
available at the start of the cycle propagate through the ADDR1MUX and
ADDR2MUX, then through the Adder, and finally through the MARMUX. From
that point on, the value on the bus is stable.
The cycle continues. The stable signal on the bus propagates on the bus,
then through the PCMUX and finally banging on the door of the PC. All this
propagation has to complete BEFORE the end of the cycle. In fact, we specify
the cycle time such that everything does complete before the end of the cycle.
At the end of the cycle, that value is loaded into the PC if LD.PC was asserted
during that cycle.
The start of the next cycle starts with that value still on the bus ...but
we really don't care since the next cycle will specify the usage of the bus,
and we will not care what is on the bus until the signals needed for that
cycle propagate to the bus.
Another example: We wish to load PC with PC+2 in cycle A.
cycle A-1 cycle A cycle A+1
| PC gets incremented by 2, propagates |
| through PCMUX, and is stable at input |
| to the PC before end of cycle |
latch the control latch the inputs
signals for cycle A to PC present at
(LD.PC/load the end of the cycle
latch the control
signals for cycle A+1
One last note. You notice that throughout the cycle the contents of PC
are used in generating the next value of PC (i.e., PC+2). At the end of
the cycle, the new value of PC is latched due to LD.PC. You might ask:
Won't that new value of PC get incremented by 2, and then go to the
PCMUX again. Answer: Sure. But now you are in cycle A+1, and the new
values of LD.PC and PCMUX have been latched.
Good luck with the rest of the course.