# State 20 of the JSRR instruction revisited

```A student writes to me and Rustam.  Not Chang Joo and Poorna?
Hmmn.

Hello Dr. Patt, Rustam

My group and I have a question about the JSRR instruction if you're
doing JSRR R7. According to the state diagram R7<-PC then PC<-BaseR
and both occurr in state 20. But how is that possible because you
will be putting the incremented PC on the bus to get it to R7 but
then you also need to load PC with the original R7.

Good question.  I hope I conveyed the insight to this question in my previous
email to the class!

To get the incremented PC onto the bus and all the way to R7, I have the
entire cycle available to me.  The value in PC is not changed throughout
the cycle.  To load PC with the original value in R7, I again have the
entire cycle available to me.  So, at the end of the cycle, the new value
of PC is banging on PC's door, and the new value of R7 is banging on R7's
door.  At the clock edge defining the end of that cycle, LD.REG and LD.PC
do their thing, and both new values get loaded.

In the appendix there is a temp variable but what does that temp
correspond to in the hardware?

It doesn't correspond to anything.  The problem with sequential algorithms
is that things happen one at a time.  So, I artificially used a variable
TEMP to convey the correct behavior of the hardware.  If I had a language
that supported parllelism better, I could have written something like:

Do in parallel {PC=R7, R7=PC}

Verilog is such a language, but I decided that would be one more thing
you would have to learn in 360N, so I didn't use it.

Is the value stored temporarily on the stack?

No, it does not exist.  Both new values are written in the same cycle in
the hardware, because hardware does do things in parallel.

Also is it true that the control signals (such as load enable signal)
are set at the end of the previous/begining of the current cycle.

NO!  The control signals are latched at the start of the cycle, but those
involving changes to state (e.g., LD.BEN) have their effect happens at the
end of that cycle.

For example for BEN <- IR[11]&N + IR[10]&Z + IR[9]&P which is state 32.

That must mean that the load enable signal for BEN must be
asserted at the end of state 35/start of 32 so that the value
is latched onto BEN in that state. Is this correct? I thought it
was but some of my group members are arguing that LD.BEN is not
asserted until the end of state 32.

Read above.  ...and my answer in the previous email.  If it is not yet
clear, ask again, ...or in class tomorrow.

Can you direct us in the right way because we're starting to
second guess everything?