```A student writes:

Dear Dr. Patt,

This question might be trivial but, I am a little confused about
when the READY bit gets set by memory. You mentioned that it takes
5 clock cycles for a memory access. However in the instructions for
LAB 3 it says "..the ready bit is asserted at the end of the fourth
cycle." So doesn't that essentially mean that it takes 4 cycles to
access memory ? Because on the 5th cycle the micro sequencer will
goto the next state right? Or does the READY signal go through a
latch and is not entirely combinational? I know that in LAB 3 it
is in a latch, but this is not made clear on the data path (Unless
the flip flop is  in the MEMORY unit.

Thanks,

<<name withheld to protect a student who thinks his question is trivial>

First, the question is not trivial.  (By definition: in 360N, if the
question is bothering you, it is not trivial. OK?)

Second, yes, memory accesses take 5 cycles, and yes, the ready bit is asserted
at the end of the fourth cycle (which is the start of the fifth cycle).

I think we are back to the same question that I answered in my two previous
emails tonight.  Signals are processed during a cycle, and the results are
latched at the end of the cycle.  In this case the important processing we
are talking about is the microsequencer and not the data path.

Suppose we initiate a memory access in the first cycle (e.g., in state 33).
At the end of the second cycle, third cycle, and fourth cycle, we are still
loading MDR with garbage, and our next state is still 33.  At the end of the
fifth cycle, we want to LD MDR with good stuff and move to the next state
(in this case, state 35).  How can we accomplish this?

The LD MDR part is easy.  Every time we execute the cycle, we load MDR with
what is on the data lines of memory.  In the fifth cycle, we want the next
state to be 35 and not 33.  The microsequencer operation needs to have the
Ready bit = 1 at the start of the fifth cycle in order for it (the usequencer)
to latch the control signals of state 35 at the end of the 5th cycle.

So, at the end of the fifth cycle, MDR is latched with memory data, and
the next state is 35.

Got it.

Yale Patt
```