What does MIO.EN mean?

A student writes:

	Hi Patt,

Hmmn.  Have not been addressed that way since I hung out with
my buddies on the street corner, with a pack of cigarettes rolled
up in the short-sleeve of my T-shirt.  ...but, whatever makes you
comfortable, I guess.  

	I thought MIO.EN was the control signal that determined 
	whether our memory
	access operation was an I/O access (1) or a memory access (0). 

Nope!  MIO.EN differentiates a mem_or_I/O access in the *current clock
cycle* from the absence of a mem_or_I/O access in the *current clock cycle*.

	However, on
	your control struction diagram you have a logic circuit feeding a mux
	controlled by MIO.EN which determines the value of MDR. 

I don't know where you got the term "control struction diagram." Based on
the context, I assume you are talking about the Data Path.

Yes, MIO.EN exactly determines the source of the MDR.  If MIO.EN is 1,
the processor is processing a load (i.e., a mem_or_I/O activity) during the
current clock cycle, so the output of the INMUX is sourced to the MDR.  If 
MIO.EN is 0, then the processor is loading MDR from the bus.  No memory or
I/O activity is taking place during this clock cycle.

	Is my
	understanding wrong? And does a YES on MIO.EN select the 
	bus output or the output from memory.

	<<name withheld to protect ...>

My response to your question is geared to your understanding of the data path 
and its control.  Note that in Lab3 (see Clarification #3), we are not 
requiring you to deal with memory-mapped I/O.  Therefore, instead of the 
ADDR.CTL.LOGIC determining whether MEM.EN or one of the I/O device control 
registers should be set, you can simply hard-wire the control signal MIO.EN 
to MEM.EN.  If we required you to implement memory-mapped I/O, then the 
ADDR.CTL.LOGIC would determine which control signals should be asserted, 
based of course, on the address in the MAR and the presence of MIO.EN.

Finally: In Lab 3 you still need to specify MIO.EN for controlling the mux you 
asked about.  In some clock cycles it will source the bus, and in other
clock cycles it will source the output of INMUX.  Part of your job is 
determining when it does each.

Good luck finishing Lab #3.

Yale Patt