memory addressiability

A student writes, and even though we have beaten to death the notion of
addressability too many times already, the nature of his question
allows me to drive home the difference between architecture (ISA) and
microarchitecture (implementation).  So, ...

	Dr Yale Patt

	I've decided to use one of my lifelines:

No decision at all, since you have an unlimited number of them, and
can not use them up.  My patience, on the other hand?  ...We'll see. :-)


	*From Appendix A:*

	*Memory addressability* Each memory location contains 
	one byte (eight bits) of information.

Yup, that is correct for the LC-3b  ...and most ISAs, as I have said many
times in class.

	My understanding is that it is a part of ISA and that 
	it can also be defined
	as the minimum size of data that can be accessed from memory? 

Indeed that is correct.  But, I prefer my definition.  It is the EXACT 
number of bits that are stored in each memory location (or, equivalently: 
at each memory address).

	In class examples it just so happens that we have 2 DRAM chips 
	each 8 bits wide and the lc3b is byte addressable.

Because a lot of today's chips actually store 8 bits at each address.

	But if I put the lc3b in a mother board with 1bit Wide DRAM chip(stupid
	example used to clarify question), 

Not at all.  EXCELLENT example, EXACTLY BECAUSE it clarifies the question.

	then how does that affect the Memory addressability? 

It doesn't.  If the chips were 1 bit wide, then I would need 8 chips ganged
together completely (exactly the same set of control signals to each of the
eight chips) to implement what we did in class with one chip.  The ISA says
the memory is byte-addressable.  If the chips I use have one bit of data on
each chip, then I need to combine (microarchitecture) 8 of them to get the same
effect as one chip that has 8 bits of data at each address.  How I combine
the chips would be totally uninteresting to the software since it would produce
the same effect.  What you are asking about is the implementation detail, 
which the last lecture dealt with in detail.  Addressability, on the other 
hand, is part of the ISA.  HOW we implement the ISA, THAT depends on what 
chips are available to us.

And, if I might add one more thing: the specification of "unaligned access" is
part of the ISA -- that is, whether it is allowed or not.  HOW we implement
unaligned accesses, (how many memory accesses, what kind of extra logic, etc.)
is part of the microarchitecture.

	Now the minimum size at each location is really 1 bit?
	What I really want to know when you say location you refer to what each
	address of the machine specifies or what each address on the memory
	specifies? I have always assumed the later.

Hopefully, the above clears this up.  If not, please ask again.

Good luck with the third program.

Yale Patt

	Thanks in Advance.
	<<name withheld to protect one who can not count lifelines>>
	"Any fool can know. The point is to understand"
	--- Albert Einstein