Does the vector load described in class end up with garbage on the bus?

A student writes:

	Dear Dr. Patt,

	I was just wondering which signals are asserted during 
	a vector load. Now,
	suppose as in SHT 1 of you handout, one were to load 2 banks of memory
	(for example locations 0,1,2, and 3) . That would mean that the "I" bit
	should be a '1'. 

Your question is very clear, so no apologies are warranted.  ...except this
statement.  I do not understand what you mean that the I bit should be a 1.
If I am understanding your email correctly, the I bit is 0 for the first 
access, and 1 for the second access.

	So, on the 1st cycle of the access, the DECODE Unit on
	your diagram asserts CE0 (to load locations 0 and 1). 


	My question to you is , will CE1 be asserted on the 2nd cycle? 


	This would ensure that the 2nd
	bank is ready at the end of the 12th cycle right? 
	(For a Cray 1 that is )


	But then wouldn't asserting CE0 and CE1 at the same time corrupt the
	values on the BUS? (Unless you assume that each 
	memory chip is designed to
	assert a Hi Z value until the ready bit is set). 

I guess you could do that.  Normally, we use buffering at both the memory
controller side and the memory side.  In fact, without buffering, how can
I assert both CE0 and CE1 at the same time since they are both outputs of
a 2-4 decoder, and you know how many outputs of a decoder can be asserted
at the same time?

So, on the memory side, we buffer the CE0, CE1, etc. signals and the chip
address, and we also buffer the outputs of the memory chips.  We also need 
a small finite state machine (mostly a counter) to keep track of when to 
negate CE0, CE1, etc. and when to tristate the output buffer of each bank 
onto the bus.

On the memory controller side, we need to buffer the address, since we are
going to have to change it each time we need to access the next memory

And, if you are still with me, I will throw in a freebie (and preview of
coming attractions -- since we will talk about vectors in a few weeks).
If you wish, you can ignore the next paragraph until we take up vector

What if we have a 4 by 3 matrix stored in sequential locations starting at
location 1000, in row major order.  That is, a00 is in 1000, a01 is in
1001, a02 is in 1002, a10 in 1003, a11 in 1004, etc.  AND, suppose we
want to load the left column of this matrix, that is the contents of 1000,
1003, 1006, and 1009.  In this case the memory controller would not 
increment the address, but rather it would add 3 to it before sending it
to the memory chips.  We call 3 the "vector stride."  We will see more of
this when we talk about vector processors. 

	I apologize if my question is not very clear.

As I already said, your question is very clear, AND very perceptive.
The drawing I made for you was intended to show the critical pieces,
not the entire story.

	Thank you ,
	<<name withheld to protect the student who wants the rest of the story>>