another question on interleaving
A student writes:
I was trying to work through the interleaving example ( on Sheet 1) we
went through in class. I understand that the BUS bits select one of the
chips in a given bank, and the Chip Addr bits select a memory
that chip. However, why do we need to have separate Row and Interleave
bits? Can't we have only one row and use 2 Interleave bits (and NO row
bit) to choose one of the banks? Is there any significance of
putting the banks in different rows?
Second question that has come in today because I left off a lot of the
"boiler plate" to the interleaving diagram. Based on what you see in the
diagram I handed out in class, this is a legitimate question.
What is missing from this diagram is the logic and buffering associated with
each bank, and the control of the buffers that are accessible from each bank.
As a start, please look at my response to the email I sent out a few minutes
Let's take the simple example shown on sht 1 of the Interleaving diagrams.
I am showing two banks. The chips enabled by CE0 and CE2 make up one bank,
the chips enabled by CE1 and CE3 make up the other bank. For each bank,
I only need one chip address register and one output buffer, for example.
If I did what you asked, I would need separate chip address registers and
output buffers for the chips enabled by CE1 and CE3, for example. Also,
more complex control logic to access the additional banks. As the number of
"rows" grows, the complication grows. Ergo, we don't usually expand the
number of banks as you suggest.
However, having said that, there are times when we would prefer to have one
(or very, very few) rows, and increase the number of banks accordingly.
I think I will save the answer to that one for the start of tomorrow's class.
Also, just wanted to confirm : Is the size of each chip given on the
second interleaving example 2^20 ?
<<name withheld to protect the student who wants only one row>>