more on unaligned accesses
A student writes:
I had a question with reference to the Simplified Block Diagram for
Unaligned Accesses in the Memory handout. Bit 28 of the address is
used as the chip enable signal in this diagram.
That is correct. So, if bit=0, the top row of chips are enabled, and
if bit=1, the bottom row of chips are enabled.
But this means that only one of the banks can be selected
corresponding to a load/store instruction. This
would not allow unaligned accesses across banks(where you would need to
select one bank for the 1st cycle and the other for the 2nd cycle).
Whoa! This is not an interleaved memory picture. There are not two banks.
Note that bits[27:2] form the address of the byte on each chip. You might
want to show more detail of each chip. That is identify where addresses
0 to F are, for example. Use the signals labeled PHYS_ADDR to help you.
You should discover that the memory addresses for this drawing (if I had
spelled them out) would be:
---- ---- ---- ----
| | 3 | | 2 | | 1 | | 0
|----| |----| |----| |----|
| | 7 | | 6 | | 5 | | 4
Suppose we are accessing the word at address 7. First access, the
chip addresses are all 000001, and what is accessed is the contents of
For the second access, we add 4 to the address register and access 8,9,10,11.
This appears to be inconsistent with the definition of unaligned
Do you now see that there is no inconsistency at all? If not, please ask
again. You (like a lot of people with far more experience than you)
confuse unaligned access with interleaving. They are two different things.
Orthogonal! You can have either or both, and if either, one without the other.
I hope I did. If not, ask again.
Thanks and Regards,
<<name withheld to protect one who confuses the two concepts>>