handling exceptions in the 4th assignment
Apparently, a number of you have raised the question as to when
an exception should be detected in the case of a control flow
change, such as JMP R0.
There are two exceptions that we are asking you to detect: protection
and unaligned access, and both could be caused by control flow instructions
and by data movement instructions.
For data movement instructions (loads and stores), I think most people
understand what causes these exceptions and where to detect them. So,
I will not spell it out here.
For control flow instructions, the question is: should the instruction
that loads the bad address into PC cause the exception or should the
exception be caught when that bad address is detected during the fetch
phase of the next instruction (i.e., because it is odd, or because it
is in system space and PSR=1). That is, our code looks like this:
A JMP R1 ; R1 contains the value B
Should we detect the exception during the execution of the instruction
at A or during the execution of the instruction at B.
We could do it either way, and there are reasons for doing it both ways.
The simplest way (and what we are asking you to do here) is to detect it
during the execution of the instruction at B. That is, when the
microinstruction does something wrong -- during the cycle when the PC loads
the address into MAR during the instruction fetch phase. In that cycle,
it is easy to check whether the contents of PC is valid (i.e., even address,
and agrees with privilege level of PSR.
By the way, we are handling these exceptions in the standard way: "BAD
program, Goodbye." In the real world, the O/S would kick the process off
the machine and load the context of the next process to be executed. In
our case, we will simply halt the machine.
I hope that helps.