A student writes:
What is the difference between backup registers in vector processors
and caches in others machines? Do they access the main memory in the
same way? Are backup registers content addressable?
<name withheld to protect the student who wants to know the difference>
The purpose of the backup registers is the same as a small cache. That is,
a place to store additional values beyond what can be stored in registers.
The big difference is that a cache is transparent to the software. That is,
the program accesses memory, and if one gets a cache hit, the data is delivered
in one cycle (for exanple), but if one gets a miss, the data does not arrive
for many cycles. Thus the time for the LD instruction is non-deterministic.
You can not count on the data arriving in one cycle, although most of the
time it does. Seymour Cray did not like non-determinism. Ergo, no cache.
The back-up registers are accessed under program control. Therefore, they
have a fixed latency and the program knows specifically when the data will
be available for subsequent use.
Some have called the back-up registers a "software-managed" cache.
Hope this helps.