The pipeline: stores and branches

A student writes:

	Dr. Patt,

	Hi. I'm looking though the pipelining stuff that we talked 
	about in class, and I realized that we never did an instruction 
	that doesn't need to store the result, like a branch or STW. 

Actually, the branch loads the PC with the target instruction (either
the fall through path or the PC+offset computation.  And the STW does
store to memory.  This normally does not create bubbles unless a 
subsequent load is to the same address as we discussed in class (recall
my "unknown address problem").

	Usually the last phase in the pipeline is to store the result 
	of the execution, but what do we do in these cases?

In the case of the store, you can assume the store to memory takes place
in the last execute stage of the store instruction.

In the case of branch, if there is no prediction, you can assume conditional
branches have to wait for the condition to be determined, and that the next
fetch can occur in the clock cycle after that condition is determined.  That
is, the PC is fed from a mux, and the condition is the select line for that
mux.

If there is branch prediction, we will assume that the hardware contains 
a BTB as described in class, so that no cycles are wasted.  That is the
next instruction after the branch is fetched in the cycle following the
fetch of the branch instruction.

	Can it skip that last stage or does it just go though it since 
	it is the next part of the pipeline? (the second is shown in 
	problem set 5 prob. #4)
	I know it doesn't really effect the time it takes to run a program ( 1
	cycle difference if it ends on a branch or STW), but I was just curious
	what really happens.

	Thanks!,
	<<name withheld to protect the curious student>>

Does this help?
Yale Patt