A student writes:
In our Problem set 5 for problem 4 ( deals with in order execution),
we had to draw the pipeline for the following set of instructions
STW R1, R6, #0 ; execution stage :3 cycles
ADD R6, R6, #2 ; execution stage :3 cycles
AND R3, R1, R2 ; execution stage :2 cycles
the pipeline in the solution shows
STW F | D | E | E | E | S
ADD F | D | E | E | E | S
AND F | D | E | E | S
Is it possible to have two write back (S) operations happening in the
same cycle for an in order machine? Wont the incomplete S operation of
the second instruction in this case clog the write back operation for
the third instruction? Is it not required for the write back stage of
third instruction to happen after write back of second in order to be
"in order "?
<<name withheld to protect one concerned about out-of-order completion>>
Our assumption on this problem set was that we could complete multiple
writebacks in the same cycle. This, of course requires multiple ports
Let me say first that it is my intent on the exam to not have you sit there
wondering how to handle some ambiguous situation.
In the real world the above problem can be avoided by fixing the length of the
pipeline so the AND has the same number of execution stages as the ADD. But,
sometimes that is not a good idea since it delays all operations to the longest
operation. In such cases, since we do not want to do that, we could have an
in-order machine with out-of-order completion of the instructions. In the above
example, if the AND had one cycle of execute (which is very common), it would
complete before the ADD. In such cases, with an in-order machine, we would
provide logic to properly sequence the completions when it made a difference.
Again, my intent is not to have you sit there wondering about such during
Good luck tomorrow.