EE 360N: Lab Assignment 6 Clarifications

  1. We will check the values of the internal pipeline latches generated by your simulator, so make sure you follow these conventions:

  2. If the D-Cache is not enabled (V.DCACHE.EN signal is 0), the data output by the D-Cache should be set to 0x0000.

  3. Control store entries corresponding to invalid opcodes (opcodes 1010 and 1011) should be set to all 0.

  4. Will you check the values in pipeline latches even if the latches are invalid?

    If the pipeline latches in a stage are invalid, our grading script is still going to check the values in the latch. The datapath of a stage performs calculations regardless of whether or not the instruction in that stage is valid (unless the valid bit is explicitly input to some logic blocks to gate the calculations). For example, even if AGEX.V is 0, the address generation logic, shifter, and the ALU will still perform calculations based on the data values in AGEX latches and control signals in AGEX.CS latch. At the end of the cycle, calculated outputs of these units will be latched into the MEM latches. Concurrently, AGEX.V is propagated to MEM.V.

  5. (Updated: 05/06/07) Because all the TRAP instruction encodings start with 1111 0000, the microinstructions in states 62 and 63 should be don't cares. However, please fill the same microinstructions into states 62 and 63 as the ones in 60 and 61 since the examples on the web say so. JMP/RET is similar to the TRAP instruction. It always starts with 1100 000, thus the microinstructions in states 50 and 51 should be don't cares. However, please fill the same microinstructions into states 50 and 51 as the ones in 48 and 49 for the same reason as the TRAP instruction. The JSRR should be treated as the same above. Please fill the microinstruction in state 16 into state 17.