Thu, 16 Apr 2009, 00:56

A student writes, with three excellent questions.
	Dr. Patt,

	I have three questions regarding the I/O lectures.

	Question 1

	In the arbitration state machine you said that we get 
	out of the transaction state (the one with two rings around it) 
	when both MSYN and SSYN are negated (MSYN'.SSYN').  But in the 
	transaction timing diagram you gave us, MSYN is not asserted 
	until later in the flow.  Shouldn't the first thing in the transaction
	timing diagram be asserting MSYN?

	M                  S
	| Address          |
	|                  |
	|             SSYN |
	|                  |
	| MSYN, CC         |
	|                  |
	|      DATA, SSYN' |
	|                  |
	| MSYN'            |

	* X' = NOT X

Actually, I could use NOT-BBSYo to terminate the transaction, but I did
say in class  I wanted to use AND (NOT-MSYN, NOT-SSYN) to terminate the
transaction.  In that case, yes, the master should assert MSYN immediately. 
So, let's correct what I said in class.  The following should work: 

	Data ----->			   	Data <------	
M			S		M			S
| BBSY,Addr,MSYN,CC     |               | BBSY, Addr, MSYN, CC  |
|---------------------->|               |---------------------->|
|                       |               |                       |
|                   SSYN|               |             Data, SSYN|
|<----------------------|               |<----------------------|
|                       |               |                       |
| MSYN', Data           |               |MSYN'                  |
|---------------------->|               |---------------------->|
|                       |               |                       |
|                  SSYN'|               |                  SSYN'|
|<----------------------|               |<----------------------|
|                       |               |                       |

	Question 2
	I think there is race condition in the controller arbitration 
	state machine when it is passing on the BGi signal down the daisy chain.

	Controller 1 goes to the BGi-out state when BGi is asserted.  This is 
	to pass on the BGi signal to the next controller (2) in the daisy 
	chain.  Controller 1 returns to IDLE when SACK is asserted.  If D is 
	asserted, the controller 1 will then go from IDLE to BRi and wait on 
	BGi.  But BGi could still be asserted because the PAU did not yet see 
	SACK asserted (and so did not have a chance to deassert BGi).  Now 
	controller 1 thinks that BGi is asserted in response to its request 
	and both controllers 1 and 2 assert SACK.  Controller 1 should not come
	out of the BGi-out state if BGi-in is asserted, right?

Outstanding!  Exactly right.  In fact, that was the example I decided not to
show you in class today, hoping one of you would pick up on it.  The solution
is simply to have the controller passing on the BGi signal return to Idle
as a result of BGi input being negated by the PAU.  That keeps the controller
that passed on the BG signal from going to Idle and then to BR before the PAU
has a chance to see SACK.

	Question 3
	You said that for RAID 0, is just one disk (or multiple disks 
	treated like one disk), so you don't get the performance benefit 
	or the reliability benefit.  Googling RAID 0 gives several 
	references that say that RAID 0 is actually striping with no 
	redundancy, so you get the performance benefit without the
	reliability benefit.  Did I misunderstand what you said in class today?

No, you are right.  I screwed up in class today.  I was so preoccupied with
the reliability material (and eager to get on to the arithmetic concepts) 
that I had forgotten that the baseline (RAID 0) provides striping.  I apologize.
Thanks for catching it.  And, hopefully, with this email message, I can correct
the misinformation I presented in class today.

Yale Patt

	<<name withheld to protect the student who should be teaching the class>