Wed, 29 Apr 2009, 20:45

Two relevant items:

First, a lecture on Sunday.  I have gotten substantial feedback that many of
you would like me to give an extra lecture on Sunday, so I will.  It will be
at 4pm and the room will be announced as soon as we confirm it.  I plan to
talk more about multiprocessing, including cache coherency, and measurement
methodology.  That will leave us with one  more lecture next Monday, and then
the final class next Wednesday.  I plan to lecture on the alternative
approaches to concurrency on Monday.  Wednesday will be my standard free-for-allwhere we will talk about whatever you want to talk about.

The lecture this Sunday is not part of the formal requirements of 360N.  
None of the material covered will be on the final exam.  It is simply some
material that you might find useful to know about.  Feel free to come or
ignore as you wish.

Second, today's exam.  It seems it does not matter how hard I try, there is
always an error in the exam that we do not catch until too late.  On today's
exam, the error was on problem 3, the cache problem.

The error involved the LRU bit of set 6.  It turns out that three of the
accesses (x364, x46C, and 265) were to that set.  If the LRU bit was a 0
before the first access, it would have had to end up a 1 after the seven
accesses.  The error is that the AFTER shows the LRU bit as a 0.

If that error caused you to miss problem 3, please send me email explaining
why.  I will take that into account when I grade problem 3.  Please do this
before the weekend, since I want to grade this over the weekend.   

And, I hope it goes without saying that I recognize that I am giving you
an opportunity to grub for points that you may not deserve.  Please resist
any temptation you might have to do so.  But, if you genuinely messed up
problem 3 because of the setting of the LRU bit, I do want to know about it
before I grade the exam.

Yale Patt