representation (ascii/two's complement etc.) switches transistors problem electrons ambiguity algorithm definiteness effectively computable terminates Abstraction Level of Transformation Processor/CPU Representation Compiler Bit Binary Byte ASCII 2's complement Floating Point Data type Carry Overflow Negative Representation Sign extension Fixed point Floating point Scientific notation Normalized form Sign-magnitude Precision Significant digits Sign bit Exponent Excess code Excess +127 Bias Floating point infinity subnormal floating point Bit vector Hexadecimal Notation vs datatype Address Logical operators, datatypes, variable Truth table Input combinations not/and/or functions Don't care Decision functions Gates Bit mask/mask bit Transistor n-type vs. p-type transistor Switch Current Gate Source Drain Ground CMOS NOT/inverter/"flip-the-bit" gate AND gate NAND gate OR gate NOR gate Complement Select line MUX Decoder Full adder Demorgan's law Black box Short circuit PLA (Programmable Logic Array) Combinational logic Sequential logic Latch R/S latch Quiescent state Write-enable State Gated latch [clock] cycle Master-slave flip-flop Memory Address space Addressability Memory Address Register (MAR) Memory Data Register (MDR) Finite state machine Inputs State variables Cycle Output Signals Moore Machine Register Control signal Loads Computational unit Address and logic unit (ALU) Temporary storage/Register file Stores Functional units Input devices Output devices Control Fetch Program counter (PC) Decode Evaluate address Execute Store result Load-store architecture Opcode Operand Instruction Instruction pointer (IP) == Progam Counter (PC) Instruction register (IR) Bus Load MAR (LD.MAR) Load IR (LD.IR) Fundamental programming constructs Sequential Conditional Iterative Intialization phase Program Destination register Instruction set Offset Conditional codes (N/Z/P) Branch Trap vector Memory Address of Instruction Operates Load Effective Address (LEA) Data Movement Instruction Control Instruction Operating System TRAP Instruction TRAP Vector Addressing Modes Immediate Operands Sign Extended Conditional Branch Fall through Jump over Backward Branch Negative Offset Bit Bucket Bit Pattern String Structured Programming Initialization Left Shift Termination of String Flow chart Halt instruction conditional branch LD instruction LDR instruction base register LDI instruction Range of offset Current PC Unconditional branch