"N" address machine
2-level adaptive predictor
access and update
access bit = reference bit. Not present in VAX
access control violation
address space
ARM incorporates multiples microarchitectures
atomic unit of processing = instruction
balance set
Big Endian v. Little Endian
branch history register
Branch prediction at factory
branch prediction
burroughs 1700 - bit addressability
bus contention vs. more number of buses - tradeoff
byte rotator
cache line (block)
capability based machines
CDC 6600 - 60 bit word size
check sum
column address strobe (CAS)
common data bus
compatibility across generations
condition codes v. no condition codes
content addressable memory (CAM)
control instructions
critical path
Cycle time v. CPI
data flow graph
data forwarding
data movement instructions
data type
delay slot
Delayed branch
design point
dynamic scheduling
ECC - single error correct double error detect (SECDED)
fixed length instruction v. variable length instruction
flow dependancy
Flynn's bottleneck
functional programming - (single assignment)
functional unit
hardware interlock
HEP (Burton Smith)
IBM RS6000: multiple sets of condition codes
Intel 432 - instructions not byte alligned
Intel 860 - RISC machine
J. E. Thointon: Control Data: CDC 6600
Jim Smith: 2 bit counter: 80%
Last time taken predictor: 70%
Load-Store ISA
memory mapped IO
MIPS - no hardware interlock
Motorola 68000
no condition codes machines - Cray
operate instructions
out-of-order execution and precise exception handling
page fault - exception
page frame number (PFN)
page frame
page mode (second access to same as first)
page table entry
parity bit check - single bit error check
pattern history table
PDP11-VAX-ALPHA - take on aligned accesses
performance equation
peter denning - working set
precise exception
predicated execution
predicated vector instructions
prefix property
register alias table
register allocation problem
reservation station (node tables)
richard hamming - ecc codes
RISC - instruction set to minimize cycle time
Robert M Tomasulo: IBM 360/91: 1965
row address strobe (RAS)
row buffer hit
row buffer
run time v. compile time
saturating counter
segment register
segmentation vs. paging
segmented model (from Intel 386)
semantic gap
seymour cray - 64 bit addressability
single instruction broken into multiple microops
spacial locality
state of machine
synchronous vs. asynchronous machines
tag store
temporal locality
Thumb ISA-fewer bits for instruction
Thumb IT instruction
tomasulo algorithm
Trade off between 2 address machine and 3 address machine
trade offs
Tradeoff between larger cache and faster cache
translation look asside buffer (TLB)
translation not valid
two address machine
unaligned access
virtual memory
vliw: itanium-EPIC
wish branch
word length
working set