We will check the values of the internal pipeline latches generated by your simulator, so make sure you follow these conventions:
If the data to be loaded/stored is a byte, set
DATA.SIZE to 0. Set
DATA.SIZE to 1 if the data to be loaded/stored is a word.
A load enable signal (LD.REG or LD.CC) should be set to 1, if the instruction is supposed to write to the structure which is load-enabled by that signal. If the instruction does not write to a structure, the load-enable signal associated with that structure should be set to 0.
If the pipeline latches in a stage are invalid, our grading script is still going to check the values in the latch. The datapath of a stage performs calculations regardless of whether or not the instruction in that stage is valid (unless the valid bit is explicitly input to some logic blocks to gate the calculations). For example, even if AGEX.V is 0, the address generation logic, shifter, and the ALU will still perform calculations based on the data values in AGEX latches and control signals in AGEX.CS latch. At the end of the cycle, calculated outputs of these units will be latched into the MEM latches. Concurrently, AGEX.V is propagated to MEM.V.