The ISA is the contract between the hardware and the software. The microarchitecture is a particular implementation of an ISA. Compiler does not need to know any information about the microarchitecture.
The first program causes x0004
to be stored in location x3000
when the assembled code is loaded into the memory. The second program causes x0004
to be stored in x3000
during the execution of the program.
The following table shows the classification of the LC-3b instructions into Operate, Data Movement and Control instructions.
Instruction | Operate | Data Movement | Control |
---|---|---|---|
ADD | X | ||
AND | X | ||
BR | X | ||
JMP/RET | X | ||
JSR/JSRR | X | ||
LDB | X | ||
LDW | X | ||
LEA | X | ||
RTI | X | ||
SHF | X | ||
STB | X | ||
STW | X | ||
TRAP | X | ||
XOR/NOT | X |
Both the second and the third instruction (never branch) can be used as a NOP. The first instruction (ADD) sets the condition codes based on the value in R1, therefore it is also not a NOP.
x1000
] + MEM[x1002
] = x1A0E
+ x0C11
= x261F
x1000
] + MEM[x1002
] = x0E1A
+ x110C
= x1F26
PUSH A
PUSH B
PUSH C
MUL
ADD
PUSH D
PUSH E
PUSH D
PUSH C
MUL
ADD
SUB
MUL
POP X
Advantages: Operate instructions only require an opcode so they can be encoded very densely.
Disadvantages: not flexible in terms of manipulating operands, more instructions required to write programs.
LOAD B
MUL C
ADD A
STORE A
LOAD C
MUL D
ADD E
STORE E
LOAD D
SUB E
MUL A
STORE X
Advantages: only a single register required, fewer instructions compared to the stack machine.
Disadvantage: not as flexible as 2 or 3-address machines. We need instructions to move data to and from the accumulator (We don't need these in a 3-address machine that supports memory-to-memory operations).
MUL B, C
ADD A, B
MUL C, D
ADD C, E
SUB D, C
MUL A, D
SUB X, X ; these two instructions emulate a MOV X, A
ADD X, A
MUL X, B, C
ADD A, X, A
MUL X, D, C
ADD X, E, X
SUB X, D, X
MUL X, X, A
MOV R2, R1
(R2 = R1):
AND R2, #0
ADD R2, R1
or
LEA TEMP ; Absolute address of TEMP in R0
ST R1, R0
LD R2, R0
....
....
TEMP .FILL xDEAD ; any garbage value
LEA LABEL
ADD R2, R3 ; Set the Condition Codes overwritten by LEA
BR R0
....
LABEL .... ; Branch to this line
Symbol | Address |
---|---|
AGAIN | x300E |
NO | x3022 |
B | x3024 |
A | x3026 |
AGAIN ADD R2, R2, R2 ADD R3, R3, #-1 BRp AGAINwith
LSHF R2, R2, #8
NOT R1, R1 ADD R1, R1, #1 ADD R2, R2, R1with
XOR R2, R1, R2
.ORIG x3000 AND R5, R5, #0 LEA R0, A LDW R0, R0, #0 LDB R1, R0, #0 LDB R2, R0, #1 XOR R2, R1, R2 BRnp NO ADD R5, R5, #1 NO HALT A .FILL x4000 .END
.ORIG x4000 |
|
The method that requires two instructions is necessary if the
subroutine we are calling is not within the range of the JSR
instruction. Note that the JSRR instruction can change the PC to any
address residing in its base register. The address in the base
register can be set to any address in memory.
For example if we have a program starting at memory location x3000 and we would like to call a subroutine starting at memory location 0xF000, there is no way to do this by just using a JSR instruction at location x3000. However, we can call the subroutine at 0xF000 using JSRR with the following sequence of instructions:
.ORIG x3000 LEA R0, SUBADDR LDW R1, R0, #0 JSRR R1 HALT SUBADDR .FILL xF000 .END
Yes, there is a difference. The program at x5000 does not save the return address from the subroutine at L2 because it uses a JMP instruction. Thus, that program will not work correctly.
A possible change that could be made:
.ORIG x5000
LEA R7,B
MAIN2 LEA R3,L2
A2 JMP R3
B HALT
;
L2 ADD R2,R1,R0
RET
Possible Solutions:
4 opcode bits, 3 NZP bits, 3 DR bits, 3 SR1 bits, 3 SR2 bits
A 2 address operation can be used instead of a 3 address. Thus, we have 4 opcode bits, 3 NZP bits, 3 DR/SR1 bits, 1 steering bit. The remaining 5 bits will either be used as 5 immediate bits, or 2 unused bits + 3 SR2 bits.
Variable instruction length ISAs have more complex decode logic. Variable instruction length ISA programs can be encoded more densely. Variable instruction length ISAs also generally imply a richer instruction set than that of a fixed length ISA. Since a richer instruction set has more instructions that directly correspond to higher level language programming constructs, the compilation process can be easier.