Wed, 24 Sept 2014, 22:11

My students,

Many of you commented after class that the example at the end pulled
everything together.  I am glad to hear that.

Some of you, however, still had some problems.  So, I have prepared
this handout.  We will also post a handout I wrote some time ago on
this topic.  Any questions on either, please let me know.

One caveat before I begin.  I am drawing these figures on an ASCII
terminal, so I do not know how good they will come out.  If they don't
I will have one of my TAs scan them in so they are clear.

Now then:

I showed you the state machine (Moore model) for the device controller.
There are inputs and outputs, as I pointed out in class.  Moore model
means the outputs are associated with the states.

The state machine shows the possible states that the device controller
can be in.

     1           2                 k     ------    k+1                n
   ------  D   ------            ------  BBSYin  --------            -------
  | Idle |--->| BRi  |--->  ... | SACK |------->| BBSYout|---> ...  |BBSYout|
   ------      ------            ------          --------            -------
      ^                                                               /
      |                                                              /
                                                   ----       ----
                                                   MSYN  AND  SSYN

States 1 to k represents the behavior before the device controller
takes control of the bus as bus master for the next bus cycle.
The bus master for the NEXT bus cycle is in state k, asserting SACK.
When the current bus master negates BBSY, this device controller moves
to state k+1, and begins the sequence needed to perform the transaction.
In this figure, state k+1 to state n are needed to accomplish the bus
transaction.  In the example below (improved on what I did on the board
today), n=k+2 (i.e., two states are needed to actually do the data transfer.

Here is the example we did in class today again, this time recognizing
that only two states are needed for the bus master, not three as I did
in class:

                  Master                     Slave
                  ------                     -----
                    |  BBSYout,MSYN,Addr,BT    |
                    |                          |
                    |                SSYN, Data|
                    |  ----                    |
                    |  MSYN                    |
                    |                    ----  |
                    |                    SSYN  |

Note that I drew the lines as horizontal.  Too difficult to do it on an angle.

The two states look like this:

   ------   -------------------------               --------------  ----
   BBSYin  |                         | SSYN, Data  |         ---- | SSYN
   ------->| BBSYout, MSYN, ADDR, BT |------------>| BBSYout,MSYN |------>
           |                         |             |              |
            -------------------------               --------------

And, of course the slave needs two states also.  What are they?

Hope the above helps.

Yale Patt