Tues, 30 Sept 2014, 10:57

My students,

Rather than tie up more class time tomorrow (unless someone has a question,
of course), I thought email would be the simplest way to make this clear.

I realize some of you are still working on lab 3.  If you are one of them,
this email can wait until after you are done.

The issue was prompted by the following student email:

> Professor Patt,
> I have a question regarding the logic located between the bus and MDR.
> When loading the MDR with data from the bus (e.g., STB and STW), the data
> passes through a logic block that relies on the DATA.SIZE signal and
> MAR[0]. Section C.5.2 explains how MAR[0] affects the store but only
> mentions DATA.SIZE after MDR is already loaded with data.
> Does this logic also check DATA.SIZE to determine what MDR is loaded with?
> Regards,
>  <<name withheld to protect the student wanting to unravel the confusion <<

As I said in class, the logic feeding the input to the MDR does not need
MAR[0].  Several students suggested that MAR[0] could be used instead of
DATA.SIZE with the same amount of logic.  They were absolutely correct!

So, the answer is: DATA.SIZE or MAR[0] is needed by that logic block as
the select line for the 8 2to1 MUXes that feed MDR[15:8].  Both are not needed!

For those who want further explanation, when I wrote Appendix C several
years ago, I was thinking that if MAR[0] is 0, I want to load bus[15:0]
into MDR.  If the instruction is a store word, all of MDR would subsequently
get written to memory from MDR.  If the instruction is a store byte, since
MAR[0]=0, only MDR[7:0] would get written.  In both cases, MDR has the
appropriate data to be written in their proper place.

On the other hand, if MAR[0] is 1, then I want to store bus[7:0] into
the odd memory location.  ...which means I want to load MDR[15:8] with
the contents of bus[7:0].

Thus, MDR[7:0] always gets bus[7:0}, and MDR[15:8] gets bus[15:8] or bus[7:0],
depending on MAR[0].  ...and this requires eight 2-1 MUXes.

When I thought about the problem two days ago, I looked at it differently,
and in fact, more intuitively in my view.  Load the MDR strictly based on
DATA.SIZE, and from there, the contents of the MDR is stored in memory.
That is, if the DATA.SIZE is 16 bits, just load MDR[15:0] from bus[15:0].
If DATA.SIZE is 8 bits, load both halves of MDR from bus[7:0].  Which half
of the MDR will get stored in memory will depend subsequently on MAR[0].
To accomplish this, we need eight 2-1 MUXes, with the select line being

Bottom line: both work.  I wrote the first one several years ago, but I like
the second one (which I thought of when I revisited the question last weekend)
better.  Both cost the same amoung of logic, as was pointed out by several
in the class.  You can do it whichever way you wish.

Good luck with the rest of the course.

Yale Patt