Thu, 23 Oct 2014, 11:37pm

A student writes:

>  Dear Dr. Patt,
>  You mentioned in the class that each chip has eight banks and each bank has
>  one set of Row address register. Here is the question. Do all of the banks
>  share one RAS? Or each of them has its own RAS.
>  In my understanding, If they share one, then we cannot make different
>  memory access on different Banks in consecutive cycles.
>  Thanks you very much.
>  Best regards,
>  << name withheld to protect the student who forgot about the bank bits >>

Indeed we could have a separate RAS for each bank, but we do not have to.
If you recall the drawing I put on the white board, one of the inputs to
each chip consisted of the three BANK bits which identify the Row Address
Register to be written, so only one RAS (and CAS) per chip is enough.

Good luck with the 4th programming lab.  I will see you in class on Monday.

Yale Patt