Newly annotated words:
The wires and associated logic associated with
interconnecting multiple entities. Usually refers to entities on chip,
for example, processors, caches, other structures. Common examples that
we will study later in the course: bus, Xbar, Omega Network, ring, tree,
ENTRY POINT (CONTROL STORE):
The starting address in control store where we store a sequence of
microinstruction which emulate the particular ISA instruction that has
FAULTS vs TRAPS :
The two basic types of exceptional events. Faults require the machine to
be backed up to the start of the instruction, and then the service routine
is called. Traps allow the machine to complete the current instruction before
the service routine is called. Example of fault: Page fault. Example of
trap: integer overflow trap.
GAg, SAs, PAp:
Variations of the Two-level Adaptive branch predictor. The two-level predictor
requires one or more branch history registers (BHR) to keep track of the most
recent branches and one or more pattern history tables (PHT) to keep track via
2-bit counters whether the branch was taken when a specific history was true.
G, S, and P refer to whether there is one history register that is used by all
branches (G for global), whether branches are broken into sets (S) such that
all branches in a set use the same history register, or each branch has its own
history register (P for PER branch). In the same way, g,s, and p take on the
same meanings, for the pattern history tables.
Instructions that are fetched during the FETCH phase of the instruction cycle
are stored in a register called the Instruction Buffer, available to be decoded
during the next clock cycle.
A variation of GAs, where the index into the PHTs is obtained by XORing bits
of the address with bits from the global history register. Has the effect of
enabling different branches that produced the same history to index to separate
entries in the PHTs and therefore, different 2bit counters. This removes a
good deal of interference.
HARDWARE PROCESS CONTROL BLOCK:
The hardware data structure that contains the state of a process that is loaded
or stored during a context switch depending on whether the process is being
swapped in (loaded) or out (stored). Intel calls it TSS.
Many programs exhibit behavior that is very different during different parts
of the execution of a program. A good *real world* example of phase behavior
is the game of chess, where very clearly there is a beginning game, a middle
game, and an end game. A simple computer example is quicksort, where the
algorithm for sorting exits the quicksort paradigm each time the number of
elements left to sort is less than some small number.
A word to describe the ease (or lack thereof) of moving a compiled program
from one machine to another. I have said many times that a compiler can do
a much better job if it knows the microarchitecture of the ISA that has been
implemented. However, optimizations based on one microarchitecture may be
disastrous on another microarchitecture, i.e., lessened portability.
results created by alus and other functional units are usually written to the
register file. Bypassing means instructions waiting for those results as
source operands do not have to wait until the result is in the register,
but can obtain that result directly from the functional unit that produced it.
List of Buzzwords:
2-LEVEL ADAPTIVE BRANCH PREDICTOR
ARBITRATION (CENTRAL, DISTRIBUTED)
BRANCH HISTORY REGISTER
BRANCH PREDICTOR (RUN TIME V COMPILE TIME)
BRANCH TARGET BUFFER
BREAKING THE LAYERS*
BUS MASTER, SLAVE
ENTRY POINT (CONTROL STORE)*
FAULTS vs TRAPS *
GAG, SAS, PAP, ...*
HARDWARE PROCESS CONTROL BLOCK*
INSTRUCTION SET ARCHITECTURE
MEDIUM OF STORAGE
OUT OF ORDER EXECUTION
PATTERN HISTORY TABLE
PRIORITY ARBITRATION UNIT (PAU)
SYNCHRONOUS, ASYNCHRONOUS BUS
VARIABLE LENGTH INSTRUCTION
VECTOR, ARRAY PROCESSING