Newly annotated words*:
Touch instruction. Some ISAs have added a TOUCH instruction (aka FETCH instruction) which the compiler inserts into the code early that does not operate on the contents of a memory location. It simply looks to see if the location is in the first level cache and if it isn't, takes the cache miss in parallel with the rest of the processing. The idea is that in an out-of-order processor, this cache miss can be serviced in parallel, so that when the data is finally needed, it is in the first level cache. For example, suppose we wish to execute LD Ri, A. The compiler would insert TOUCH A earlier in the code. In this way, when the processor reaches LD Ri,A, the location A is in the first level cache.
Floating point format involves a radix. Two good reasons for using 2 as the radix: (1) wobble is minimized for floating point data, and (2) we don't have to store the most significant bit for normalized numbers, since it is a 1.
Redundancy. Extra work that is done, i.e., more work than is absolutely necessary. Two good examples of why we would want to do such extra work. One we talked about in class: if we have p processors, we may want to do some extra work on the additional processors in order to get the job to finish quicker. One we did not talk about in class: fault tolerance, or what is today called high availability systems or resilient systems. That is, systems that operate correctly in the presence of things not working properly. A case in point is Triple Modular Redundancy (TMR). If we do the task once and something is broken, we get the wrong answer. So, we do it three times and compare the three answers. If one part is broken, we still get the right answer. For systems that must not go down, redundancy can help.

List of Buzzwords:
Tag Store Entry
Victim/ Next Victim
Activation records
Stack frame, applicaton environment
allocate on write miss
sector cache
instruction cache
data cache
cold start after context switch
virtually indexed, physically tagged
touch instruction*
multi-level cache
tradeoff for separate vs shared data/instruction L2 cache
fixed point
floating point
fixed point vs integer
long integer
signed magnitude
2's complement vs 1's complement
residue arithmetic
write back buffer
cache back translation
Booth algorithm
radix of 16 (e.g. PowerPC)
Exponent, fraction, sign bit
IEEE floating point
Normalized numbers
excess code
Two reasons for radix of 2*
gradual underflow
round up / down/ towards 0 / unbiased nearest
finite number
Exceptions: inexact, underflow, overflow, divide by 0, invalid
sticky bit or signaling bit
ACMP, asynchronous heterogeneous cores
granularity of concurrency
tightly coupled vs loosely coupled
Amdahl's law
Speed up
Super linear speed up
effect of sigma in Amdahl's law
Multim processing overhead
interconnect, cost, latency, contention
bus, crossbar, ring, tree, x-tree
HyperCube, mesh, banyan tree, omega network
cache coherency
cache coherency in case of 1 processor with a DMA
solution to cache coherency, invalidate or update
snoopy cache
synapsis 3 state FSM
Goodman, Patel schemes
Illinois protocol
write once
directory cache
write once
sequential consistency