The University of Texas at Austin
Department of Electrical and Computer Engineering

Problem Set 3

EE 382N – Spring 2014
Yale N. Patt, Instructor
Faruk Guvenilir, Milad Hashemi, TAs
Due: Wednesday, February 19th, 2014, beginning of class

Part 1

Augment your datapath to handle the following:

Notes for SIMD instructions:

Notes for instructions operating on segment registers (these specifications override the x86 manuals for the purposes of this assignment and the project):

Show all control signals needed to control the augmented datapath. In Problem Set 4 we will start specifying the logic needed to produce those control signals.

Part 2

Enter the additions of Part 1 above into your Verilog implementation.

Part 3

To test your augmented specification, select five more instructions with appropriate addressing modes and prefixes (at least one of them must be an SIMD instruction). Calculate the number of cycles required to execute each of these five instructions. Your results will depend on your choices, of course. For purposes of this assignment, assume 10 ns cycle time, single-cycle cache access, 100 ns memory access time, data cache hit ratio of 0.80, instruction cache hit ratio of 0.95 and no page faults.