Mon, 16th Nov 2015, 03:09 Re: Question on data path

A student writes.  ...and while too late to help with the second midterm,
it is important stuff so I am sharing it with all of you since it could
very well be useful for the Final Exam and what comes after EE306.

> Dr. Patt,
> I understand the state machine and most of the microarchitecture of the
> LC-3, but when I come across questions that ask me to fill in what certain
> parts are doing, such as value of LD.PC LD.REG ALU and  ALUK, I don't know
> how to come up with the right values. How should I be thinking about this?
> Thank you,
> <<name withheld to protect the student who clearly missed a step in
> learning the data path>>

And another student who gives himself a signature, clearly indicating
that he enjoys his own sense of humor better than mine.

I assume you have looked at what we call the "Define File" which specifies
each code for each control signal.  For example, ALUK consists of two bits
and so it can specify one of four codes: ADD, AND, NOT, and PASS_A.
LD.REG is a one bit field, so it can specify one of two codes: Load and
Don't Load.

You look at the data path and ask yourself what do I want to happen in
this clock cycle.  Suppose you want MAR to be loaded with the contents
of the PC.  What do you need in the way of control signals to make that
happen.  You need the contents of the PC on the bus.  Therefore, GATE.PC
must be GATE and must not be Do_Nothing.

Incidentally, that means all other GATE.xx signals must be Do_Nothing.
Do you understand why?

So the PC is on the bus.  Where does it want to go?  Into the MAR.
Therefore LD.MAR must be Load and not be Do_Nothing.

Hope this helps.

Good luck on the final exam.

Yale Patt