Mon, 22 September 2016, 20:48

Subject: Re: 460n Homework 2 problem 2 -- Note: Problems 1,2,14-18 postponed

A student writes (and calls attention to two things):

> Dear Dr. Patt,
> I just wanted to get clarification on this sentence on Homework 2 problem 2:
> "All execution units (including the load/store unit) are fully pipelined"
> In the previous problem, we had to accommodate a case where there was only
> 1 adder. Can I make the assumption that there are multiple adders based off
> of the above sentence? Because if there is only 1 adder, I would have to
> finish executing the first add instruction before the second in the case
> where there are two consecutive add instructions:
>                              ...
>          ADD   R6, R6, #2
>          AND R3, R1, R2
>                              ...
> Regards,
> <name withheld to protect the student who will have to wait to solve Prob 2>>

As I said, two things.

Thing 1. Problems 1,2 and 14-18 should not have been assigned.  We have not
discussed the relevant topics yet in class, and I do not expect you to solve
problems until I try to give you the insights into those problems in class.

Thing 2. The student misunderstands the notion: "All execution units are
fully pipelined."  This also will be explained in detail when we discuss
executing instructions out of program order in a few weeks.  Still, I feel
compelled to tell you what fully pipelined means in the context of a functional
unit.  Suppose an operation takes four clock cycles and is fully pipelined.
That means the operation can be broken down into four parts.  Call them OP1,
OP2, OP3, OP4.  One can (if one wishes to) initiate that operation
every clock cycle.

In cycle 1, the first operation does OP1.
In cycle 2, the first operation does OP2, the second does OP1.
In cycle 3, the first does OP3, the second does OP2, the third does OP1.


Got it!

Good luck with the rest of the course.

Yale Patt