Sat, 1 October 2016, 1:46

```

A student writes:

> Hi Dr. Patt,
>
> I have a question about memory interleaving. Let's use the problem 4 in
> problem set 2 as the working example.
>
> Interleaving gives us the ability to access memory in different banks at
> the same time. My understanding of this is when you access A[0][7], A[1][7]
> .. A[7][7] will be ready when A[0][7] so that we do not have to wait.
> However, one of my friends told me that when we access A[0][7],
> interleaving gives us the ability to access A[1][0] right after that if we
> want without waiting 10 cycles. The two access do not need to have the same
> chip address. His point is different banks are different hardware unit, and
> thus, we can access them as we want as long as they are not busy.
>
> I would like to have you clarify this point so that we can understand this
> better.
>
> --
> Best,
> <<name withheld to protect the student who has a smart friend>>

Your friend is correct.  Some of the bits of the address, as Faruk told you
when he gave that lecture, are "bank bits."  Thus one address goes to only
one bank.

Since A[0][7] is in a different bank than A[1][0], I can do the following:

In cycle 1, you initiate the access of A[0][7].
In cycle 2, you initiate the access of A[1][0].
...
In cycle 10, you get the data from A[0][7].
In cycle 11, you get the data from A[1][0].

With interleaving, you pay the 10 cycle latency once.

It is often useful to access a sequence of memory locations, such as
A[0][7]...A[7][7].  If this were the case,

In cycle 1, you initiate the access of A[0][7].
In cycle 2, you initiate the access of A[1][7].
In cycle 3, you initiate the access of A[2][7].
In cycle 4, you initiate the access of A[3][7].
In cycle 5, you initiate the access of A[4][7].
...
In cycle 10, you get the data from A[0][7].
In cycle 11, you get the data from A[1][7].
In cycle 12, you get the data from A[2][7].
In cycle 13, you get the data from A[3][7].
...

Again, you pay the latency cost once.

By the way, if the latency is less than the degree of interleaving, you
can pay the latency cost only once even if you are accessing a large number of
sequential addresses.  Do you see why?

Yale

```