Thu, 13 October 2016, 22:42

A student writes:

> Hi Dr. Patt,
> In section C.5.2, there are two statements that seem to contradict what
> value should be loaded into the MDR after states 23 and 24.
>    1. *A MUX selects either SR[15:0] or SR[7:0]’SR[7:0], based on MAR[0].*
>    2. *Recall that if DATA.SIZE is BYTE, MDR was previously loaded with
>    SR[7:0]’SR[7:0].*
> If the MAR[0] is 0 and DATA.SIZE is BYTE, do we load SR[15:0] or
> SR[7:0]'SR[7:0] into the MDR? I understand that either way the store
> instructions will work correctly, but I want to make sure my MDR value is
> correct for lab 3.
> Thanks,
> <<name withheld to protect the student who found an inconsistency>>

Thank you for pointing out this inconsistency.  You are absolutely right:
(a) the sentences conflict as to what MDR contains at the end of state 24,
and (b) it does not matter, since both ways will cause the LC-3b to operate
in accordance with the ISA.

However, I do not like inconsistencies, and I am particularly pleased that
you pointed it out.  It turns out that I got carried away and provided too
many control signals, and I am using this email to correct the text of
Appendix C:

Consider the Logic block that takes its input from the bus and sends its
output to the MUX controlled by MIO.EN.  Two control signals are applied
to the logic block, DATA.SIZE and MAR[0].  MAR[0] is unnecessary, as described
below, and should be deleted.

Input from the bus to the Logic Block is the contents of SR.

If we are in state 23, we are performing STW. which means DATA.SIZE is word.
MDR gets loaded with the contents of SR, and in state 16, the word gets stored
to memory.

If we are in state 24, we are performing STB, which means DATA.SIZE is byte.
MDR gets loaded with two copies of the byte in SR[7:0], one copy in MDR[7:0]
and one copy in MDR[15:8].  In state 17, the WE LOGIC will assert WE1 or WE0,
depending on MAR[0] and DATA.SIZE.

Good luck finishing Lab 3 by Sunday night.

Yale Patt