The University of Texas at Austin
Department of Electrical and Computer Engineering

Project Specification

EE 382N – Spring 2016
Yale N. Patt, Instructor
Ben Lin and Stephen Pruett, TAs


Please consult the list of instructions to be implemented . The following is a quick summary of that list:

OpcodeManual pageVariations
ADD3-22All variations
OR3-32All variations
BTC3-57All variations
CALL3-59All variations except m16:16 and m16:32
CLD3-73All variations
CMOVC3-81All variations of CMOVC
SCAS3-96All CMPS variations
CMPXCHG3-107All variations
DAA3-182All variations
HLT3-324All variations
IRETD3-354IRETD variation for 32-bit stack
Jcc3-362All JNE and JNBE variations (4 total)
JMP3-366All variations except m16:16 and m16:32
MOV3-441All variations except moffs format
MOVQ3-486All variations except xmm format
NOT3-517All variations
PADDD3-537All variations except xmm format
POP3-599All variations
PINSRW3-653All variations
PUSH3-663All variations
REPNE SCAS3-687Repeat CMPS variation only
RET3-690All variations
SAL3-703All variations of SAL
SAR3-703All variations of SAR
STD3-745All variations
XCHG3-803All variations

Note that the NOP instruction is a special case of the XCHG instruction.


Addressing Modes

Data Types

General Issues


An effective address is computed from the instruction, e.g., a base plus displacement specified with the Mod r/m byte.

A linear address is calculated by summing the effective address with the appropriate segment register having been shifted 16 bits to the left for a total size of 32-bits.

Main Memory

Main memory is 32KB in size. The exact configuration is per your design. Please use the SRAM parts from the library to construct your main memory.


Instruction and data cache size is limited to 1KB of data storage total. The exact configurations are per your design; however, the cache line size must be greater than your data bus width. Please use RAM parts from the library to construct your tag and data stores. You may use register parts to construct the valid bits, so that they can be initialized to zero easily.

The Bus

A bus must connect the processor, main memory and your I/O devices. Its width and arbitration scheme are per your design; however, the maximum data bus width is 32 bits.

Fan out

When using the gates from the library, each gate is itself able to drive up to 4 other gates. If you need to drive more than 4 inputs buffering is required. We have provided several buffers in the library modules. Please adhere to the following rules while providing buffering:

  • The output is defined as the output of a gate OR the output of a behaviorally defined module in a lib file.
  • The input is defined as an input of a gate OR an input of a behaviorally defined module in a lib file.
  • No buffering is required if an output drives up to 4 inputs only. Buffering is required if an output drives more than 4 inputs.
  • You should buffer an output using bufferH16$ or bufferHInv16$ if the output drives upto 16 inputs only.
  • You should buffer an output using bufferH64$ or bufferHInv64$ if the output drives upto 64 inputs only.
  • You should buffer an output using bufferH256$ or bufferHInv256$ if the output drives upto 256 inputs only.
  • You should buffer an output using bufferH1024$ or bufferHInv1024$ if the output drives upto 1024 inputs only.
  • An output can drive ONLY ONE of the high-load buffer modules (i.e. bufferH16$, bufferHInv16$, bufferH64$, bufferHInv64$, bufferH245$, bufferHInv256$, bufferH1024$, bufferHInv1024$).
  • You should not be building your own buffer trees. If a need arises, please talk to us.
  • Segmentation

    Each segment has a constant (hardwired) segment limit associated with it. When an effective address exceeds the segment limit a general protection exception is taken (see Interrupts and Exceptions below for details). Be advised that when accessing a word, double word, or quad word, all the bytes in the data must fall within the segment limit.

    Default Segment Register Details

    As explained in Section, Table 3-2 of the Basic Architecture manual, SS, not DS, is the default segment register for memory accesses involving [EBP] + disp8 and [EBP] + disp32 addressing modes, as well as when ESP is used as the base register in the SIB byte (remember, you do not need to implement SIB addressing modes using EBP as the base register).

    Virtual Memory

    You are required to implement parts of a virtual memory system as specified below.

    The page size for your project is 4KB.

    A Translation Lookaside Buffer (TLB) will be used to translate between virtual page numbers and physical frame numbers. Each TLB entry will contain at least the following flags: a valid bit, a present flag, and a read/write flag. Note a translation can be valid without the page being present in main memory, hence the valid and present flags. Depending on your design, you may or may not need a PCD flag (Page-level Cache Disable) for your I/O devices. See I/O Devices below.

    A page can be in the “read only” state or in the “read or write state,” as indicated by the read/write flag.

    The TLB will hold 8 entries, 6 of which will be hardcoded to values specified by your TA. The other two entries are per your design, e.g., memory mapped I/O or other project specific purposes.

    If the processor tries to write a read only page, then a general protection exception is taken. If the processor tries to access a page not present in the TLB or a page not present in physical memory, then a page fault is taken. (Note the abstraction: you are not required to implement the x86 page directory table for this project.)

    Note that multiple virtual pages could potentially map to the same physical frame.

    I/O Devices

    You are required to implement at least one simple and one complicated I/O device for your project. See the LC-3B documentation (LC-3B ISA, LC-3B Microarchitecture) for simple examples of memory mapped keyboard and monitor registers. An example of a more complicated I/O device is a DMA controller. Be advised that memory addresses that correspond to memory mapped I/O devices cannot be cached. You can use the TLB to indicate that a page cannot be cached by setting the PCD flag (Page-level Cache Disable) in the TLB. In this case, you will issue the request to main memory directly.

    Interrupts and Exceptions

    You are required to support at least one external interrupt from one of your I/O devices. The two exceptions that you are required to support are the general protection exception and page fault. Note that both instruction and data accesses may cause these exceptions.

    General protection exceptions are caused by writing to a read only page or when computing a memory operand with an effective address outside the CS, DS, ES, FS or GS segment limit. Note that accessing memory outside the stack segment(SS), limit causes a Stack Segment Exception which is not required for this project.

    Page faults are caused by accessing a page that is not in the TLB or not present in physical memory.

    There will be no nested interrupts/exceptions.

    The procedure for transferring control to the interrupt and exception handler is the following:

    1. Push EFLAGS.
    2. Push CS.
    3. Push EIP.
    4. Determine the address of the Interrupt Descriptor Table (IDT) entry that contains the far pointer that points to the relevant service routine.
    5. Load the new CS and EIP values and begin executing from the new location.

    The IRETD instruction will appear at the end of the interrupt service routine and will pop the EIP, CS and EFLAGS registers.

    The far pointer pointing to the service routine is found by indexing into the IDT with the interrupt or exception vector.

    The IDTR register contains a pointer to the base address of the IDT. The value in the IDTR is a linear address. The IDTR register is actually a 6-byte register, where the first 4 bytes are the base address of the IDT and the final 2 bytes are the limit of the base address. You are not required to implement limit checking on the IDT. Therefore the first 4 bytes are all that you need to worry about for this project. IDTR will be hardwired at initialization time and won't change while the processor is running.

    The vector number for the page fault is 14 and the vector number for general protection exception is 13.

    If an instruction causes both a General Protection exception and a Page Fault, your machine should handle the General Protection exception and ignore the Page Fault.

    Interrupt Descriptor Table Details

    Make sure that your design uses the Interrupt Descriptor Table entry format described in Section 5.11, Figure 5-2 of the System Programming Guide.