Instructions:
You are encouraged to work on the problem set in groups and turn
in one problem set for the entire group. Remember to put all
your names on the solution sheet. Also, remember to put the name
of the TA and the time for the discussion section you would like
the problem set turned back to you. Show your work.
For example, in part a, the missing item is X. That is 0 OR 0 = 0 and 0 OR 1 = 1.
A B C D __|______|__ __|______|__ \ 0 1 / \ 0 1 / \_________/<------ S0 \_________/<------ S0 |_____________ _________| ___|_____|__ \ 0 1 / \________/<------ S1 | FYou require 3 muxes. First, the input are A and B and the select line is S0. Second, inputs are C and D and the select line is also S0. Third, is a mux where both its inputs are the outputs of the first two muxes and select line is S1.
B) Implement F = A xor B using ONLY two 2-to-1 muxes. You are not allowed to use a not gate (A' and B' are not available).
1 0 __|______|__ \ 0 1 / \_________/<------ B B | ___|_____|__ \ 0 1 / \________/<------ A | F
E = ((A AND B) AND (C AND D) ) AND E)
For the OR gate generating the Ci+1, connect the 4 outputs: 011, 101, 110, and 111 from the decoder to the OR gate. Connect the remaining 2 inputs of the OR gate to 0.
Design the combinational logic circuit for an elevator controller such that the
option to go up or down by only one floor is disabled. Assume that the building
the elevator is in has 4 floors. Your inputs are the current floor and the next
requested floor. The output from the controller should be the next floor to go
to. Please show the full truth table for the elevator controller.
Since there are four floors, you will need 2 bits to represent a floor. Let
the logic variable C[1:0] represent the current floor, R[1:0] represent the
requested floor, and D[1:0] represent the floor the elevator should go to
given a current floor and a requested floor. Shown below is the truth table
for this combinational logic circuit.
C1 C0 R1 R0 | D1 D0 ------------------- 0 0 0 0 | 0 0 0 0 0 1 | 0 0 0 0 1 0 | 1 0 0 0 1 1 | 1 1 0 1 0 0 | 0 1 0 1 0 1 | 0 1 0 1 1 0 | 0 1 0 1 1 1 | 1 1 1 0 0 0 | 0 0 1 0 0 1 | 1 0 1 0 1 0 | 1 0 1 0 1 1 | 1 0 1 1 0 0 | 0 0 1 1 0 1 | 0 1 1 1 1 0 | 1 1 1 1 1 1 | 1 1
Question 9 was moved to problem set 3.
Draw the transistor level circuit of a 2 input XOR gate
A |
B |
G |
E |
L |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
b. Implement G, E
and L for a 1-bit comparator using AND, OR, and NOT gates.
G = AB' , L = A'B , E =
A'B' + AB
c. Figure 3.41 performs one-bit
comparisons of the corresponding bits of two unsigned integer A[3:0] and B[3:0]. Using the 12 one-bit results of these
4 one-bit comparators, construct a logic circuit to output a 1 if unsigned
integer A is larger than unsigned integer B (the logic circuit should output 0
otherwise). The inputs to your logic circuit
are the outputs of the 4 one-bit comparators and should be labeled G[3], E[3],
L[3], G[2], E[2], L[2], ... L[0]. (Hint: You may not need to use all 12
inputs.)
Y = G[3] + E[3]G[2] + E[3]E[2]G[1] +
E[3]E[2]E[1]G[0]
One of Professor Patt's students is always late to meetings, so Professor Patt wants you to design an alarm clock to help his student be on time. Your job is to design a logic circuit whose output Z is equal to 1 when the alarm clock should go off. The circuit will receive four input variables (A, B, C, D) that answer four different yes/no question (1=yes, 0=no):
A <= Is it going to be sunny today?
B <= Is it the weekend?
C <= Is it 7:00am?
D <= Is it 9:00am?
Professor Patt wants the alarm clock to go off if it's sunny and it's either 7:00am or 9:00am. The alarm clock should go off if it's the weekend and it's 9:00am. The alarm clock should also go off if it's not the weekend and it's 7:00am. Write the truth table and draw a gate-level diagram that performs this logic.
A B C D | ALARM ------------------- 0 0 0 0 | 0 0 0 0 1 | 0 0 0 1 0 | 1 0 0 1 1 | x 0 1 0 0 | 0 0 1 0 1 | 1 0 1 1 0 | 0 0 1 1 1 | x 1 0 0 0 | 0 1 0 0 1 | 1 1 0 1 0 | 1 1 0 1 1 | x 1 1 0 0 | 0 1 1 0 1 | 1 1 1 1 0 | 1 1 1 1 1 | x
In class, we showed that NOT((NOT A) AND (NOT B)) == A OR B using their truth tables. This equivalence is known as DeMorgan's law. Similarly, show that NOT((NOT A) OR (NOT B)) == A AND B.
A B | NOT A | NOT B | (NOT A) OR (NOT B) | NOT ((NOT A) OR (NOT B))| A AND B ---------------------------------------------------------------------------- 0 0 | 1 | 1 | 1 | 0 | 0 0 1 | 1 | 0 | 1 | 0 | 0 1 0 | 0 | 1 | 1 | 0 | 0 1 1 | 0 | 0 | 0 | 1 | 1
Draw the transistor level circuit of a 3 input majority gate.