These are the buzzwords for this semester. See the Glossary of Buzzwords from Fall 2005 to Present for explanations of each buzzword.

List of Buzzwords:
Device
ISA
atomic unit
Auto increment (post increment)
operand specifier
Basic block
algorithm
ASCII
Byte addressable
circuits
clock cycle
data type
1's complement
2's complement
Floating point
Endianness
levels of transformation
microarchitecture
Moore's Law
Hardware
Compiler
Bandwidth problem
Role of the Architect
Critical Path Design
Bread and Butter Design
Balanced Design
Profiling
Instruction supply
Datapath
Data supply
Accelerators
3D chips
speculative execution
unaligned access
addressing mode
condition codes
instruction cycle
** sign-extend
hardware interlocks
physical memory
load/store architecture
fixed length vs. variable length
out-of-order execution
0,1,2,3 address machines
RISC
VAX
overflow
pseudo-op
control signal
control store
decoder
microinstruction
microsequencer
pipelining
Branch prediction
Compile time predictor
predicated execution
hammock
program phases
last time taken predictor
2-bit saturating counter
Branch History Register (BHR)
2-level adaptive predictor
GAg (and variations)
Global/set/per 2-level predictor
branch misprediction penalty
context switch
HEP (Burton Smith)
Tomasulo's algorithm
Scoreboard bit
Reservation station
register renaming
Data forwarding (data bypass)
stale data
Register alias table
Architectural/physical registers
data flow graph
In-flight instructions
Node table
Hashing functions
g-share predictor (Scott McFarling)
Interrupt
Exception
Fault, Trap
consistent state
Service routine (handler)
SRAM
DASD
Refresh (in DRAM)
DRAM
parity
hamming code
ECC
Page mode
Volatile/Non-Volatile
Bitline
Word line
Row Buffer
Byte-on-Bus bits
chip enable
Address Space
Bank
Interleaving
Byte rotator