These are the buzzwords for this semester. See the Glossary of Buzzwords from Fall 2005 to Present for explanations of each buzzword.

List of Buzzwords:
Device
ISA
atomic unit
Auto increment (post increment)
operand specifier
Basic block
algorithm
ASCII
Byte addressable
circuits
clock cycle
data type
1's complement
2's complement
Floating point
Endianness
levels of transformation
microarchitecture
Moore's Law
Hardware
Compiler
Bandwidth problem
Role of the Architect
Critical Path Design
Bread and Butter Design
Balanced Design
Profiling
Instruction supply
Datapath
Data supply
Accelerators
3D chips
speculative execution
unaligned access
addressing mode
condition codes
instruction cycle
** sign-extend
hardware interlocks
physical memory
load/store architecture
fixed length vs. variable length
out-of-order execution
0,1,2,3 address machines
RISC
VAX
overflow
pseudo-op
control signal
control store
decoder
microinstruction
microsequencer
pipelining
Branch prediction
Compile time predictor
predicated execution
hammock
program phases
last time taken predictor
2-bit saturating counter
Branch History Register (BHR)
2-level adaptive predictor
GAg (and variations)
Global/set/per 2-level predictor
branch misprediction penalty
context switch
HEP (Burton Smith)
Tomasulo's algorithm
Scoreboard bit
Reservation station
register renaming
Data forwarding (data bypass)
stale data
Register alias table
Architectural/physical registers
data flow graph
In-flight instructions
Node table
Hashing functions
g-share predictor (Scott McFarling)
Interrupt
Exception
Fault, Trap
consistent state
Service routine (handler)
SRAM
DASD
Refresh (in DRAM)
DRAM
parity
hamming code
ECC
Page mode
Volatile/Non-Volatile
Bitline
Word line
Row Buffer
Byte-on-Bus bits
chip enable
Address Space
Bank
Interleaving
Byte rotator
Virtual memory
pages
Frames
Thrashing
Page fault
Resident page
PTE (Page table entry)
Page table
Modify bit
Protection bit
Levels of privilege
Virtual Address Translation
ACV/ TNV checks
Disk arm / track / Rotation / Seek
Reference bits
System space
Variable page size
Intel variable page sizes
2-level mapping in virtual address translation
Segmentation
VAX P0 (program) / P1 (control) space
Working Set
Balance Set
Page Table Base registers
System Base Register
Walking the page table
TLB (Translation lookaside buffer)
TLB Hit rate
Real Address
linear address space
Segmented Model
Segment Registers
Tag store
Logical Address
Intel Page directory, Page table
Task State Segment (TSS)
Instruction prefixes of x86
Associative memory
context switch
CAM
Cache line (block)
Spatial locality
temporal locality
tag, index, offset bits
Tag/data store
Direct-mapped cache
Cache hit/miss
Set-associative cache
Fully-associative cache
Replacement policy
FIFO (first in first out)
LRU (least recently used)
victim/next victim
3-bit pseudo-lru scheme
dirty bit
sector cache
Instruction cache
Data cache
Prefetching
Valid bit (in cache)
writeback/write through
Allocate on write miss
Virtual Cache (virtually-indexed, virtually-tagged cache)
Cold start
virtually-indexed, physically-tagged cache
Device controller
Disk terminology
Track and cylinder of the disk
Rotation time
seek time
Disk block
Asynchronous/synchronous buses
handshake
Arbitration
Central Arbitration
distributed Arbitration
PAU (priority arbitration unit)
Bus grant
bus request
daisy chaining
Multiplexed Address and Data Bus
Bus Master
slave
Race Condition
DMA
Pending Bus
Split-Transaction Bus
Signed Magnitude
1's complement
2's complement
BCD
DAA instruction
residue
relatively prime
Chinese remainder theorem
Multiplication as a sequence of shifts and adds
Booth Algorithm
Floating point
Overflow
Rounding
Fixed point
Integer
Mantissa
Binade
Inexact exception
excess / bias
Unit in the last place (ULP)
4 different ways of rounding
1- round towards 0
2- round up
3- round down
4- round unbiased nearest
wobble: 2-1 ulp ratio on binade boundaries
Floating point exceptions
1- inexact
2- underflow
3- invalid
4- overflow
5- divide by 0
subnormal numbers
gradual underflow
NaN Not a Number
(dynamic/static) instruction stream
superscalar
Flynn's bottleneck
superpipelined
SIMD (data parallel)
Vector processor
Array processor
MIMD
VLIW
Vector register
backup registers
Loop buffers
vector chaining
Vector stride register
Lockstep
trace scheduling
skewed branches (read "trace scheduling" in glossary)
PTU = prepare to undo instruction (read "trace scheduling" in glossary
decoupled access/execute (DAE)
dataflow graph
Data driven execution
Asynchronous execution of nodes (see dataflow)
fire when ready
Dataflow tokens
Conditional nodes
Relational nodes
Granularity of concurrency
Intra-instruction parallelism (see above)
Inter-instruction parallelism (see above)
Multiprocessor
floating point Co-processor
accelerator
Shared global memory
Multi-computer network (see multiprocessor)
Tightly Coupled
loosly coupled
Serial bottleneck
Amdahl's law
speedup
Buzbee's observation
Efficiency of a multiprocessor
Utilization of a multiprocessor
Redundancy
Memory contention
interconnect (see handout for interconnect terms)
Bus
Crossbar
Ring
tree
Mesh
hypercube
Interconnect cost / latency / contention
Omega network
Cache coherency
Broadcast update
Broadcast invalidiate
Snoopy cache
Inclusion (property of caches)
Directory
Memory consistency
Speedup
Utilization
Redundancy
Efficiency