Y. N. Patt, Instructor
Francis Tseng, Seema Prasad, TAs
August 25, 1999
August 25: First class, Introduction to the course. Review the syllabus, discuss requirements of the course. Introduction to the computing environment that will be used in the course. Introduction to the field of Computer Architecture and microarchitecture.
August 30: Case study, an example ISA: the LC-2. The LC-2 ISA. Assembly language syntax of the LC-2. Introduction to Assemblers.
August 31 (tentative): Discussion session.
September 1, 8: Case study, an example microrchitecture, the LC-2. Specification of the LC-2 data path, control, state machine, microsequencer, the define file, microcode. This block of information is intended to provide a detailed comprehensive understanding of how the microarchitecture of a processor emulates the instruction set architecture.
Lab Assignment 1 due, September 10.September 13: Physical Memory. SRAMS, DRAMS, interleaving, unaligned accesses.
September 14 (tentative): Discussion session.
September 15: Virtual Memory. Address translation, Page Tables. Protection and access. TLBs. Paging and Segmentation.
Problem Set 1 due, September 17.September 20: No class. Students expected to spend time on Prog. 2.
September 21 (tentative): Discussion session.
September 22: A step up: What is computer architecture (the ISA: opcodes, addressing modes, data types)? Zero address machines, one address machines, two address machines. What is microarchitecture (the data path and its control, and the microsequencer)? Overview of the basic elements of each, including structure of memory (addressing and addressibility), instruction processing, models of execution (including the Von Neumann model). The RISC phenomenon -- what it was, what it wasn't. Codes (including parity, ECC, and ASCII). System architecture issues (secondary storage, I/O.
Problem Set 2 due, September 24.September 27: Review for first hour exam.
September 29: Exam 1
October 4, 6: Cache Memory. Caches and Cache Design. Tag store and Data Store. Set Associative, Direct Mapped, and Fully Associative, Set Size, Block Size, Write Through vs. Write Back, Replacement Algorithms, Sector Caches, Uniprocessor consistency, Virtual vs. Physical, Unified vs. Split.
October 5 (tentative): Dsicussion session.
Lab Assignment 2 due, October 8.October 11: Interrupts and Exceptions. Types, similarities, differences. Causes, 11tification, handling, masking.
October 12 (tentative): Discussion session.
October 13: I/O (interrupt driven, polling, DMA, i/o processors). I/O Buses (asynchronous and synchronous). Arbitration (central vs. distributed). Bus transactions. An example.
October 18: Introduction to Performance Enhancement. Pipelining.
October 19 (tentative): Discussion session.
October 20: Performance Enhancement, continued. Out-of-order execution.
Problem Set 3 due, October 22.October 25: Performance Enhancement, continued. Vector processing.
October 26 (tentative): Discussion session.
October 27 Performance Enhancement, continued. Branch Prediction.
Lab Assignment 3 due, October 29.November 1: Integer Arithmetic. A special case of fixed point arithmetic. 2's complement, 1's complement, BCD, long integers, residue arithmetic. Multiplication, Booth's algorithm.
November 2 (tentative): Discussion session.
November 3: Floating Point Arithmetic. Range vs. Precision. The IEEE Standard. Formats, gradual underflow, rounding modes, infinities, NaNs, wobble.
November 8, 10: Case Studies: The Microarchitectures of the latest high performance microprocessors.
November 9 (tentative): Discussion session.
Problem Set 4 due, November 12.November 15: Review.
November 17: Exam #2.
November 22: Introduction to Intellectual Property. Discussion of the various ways intellectual property is protected, including patents and copywrites. We will examine the various parts of a relevant patent.
November 23 (tentative): Discussion session.
November 24: TBA
November 29: Measuring Performance. Basic metrics (e.g., SPEC95) and fundamental abuses.
November 30 (tentative): Discussion session.
December 1: Other Attempts to Exploit Concurrency, SIMD (both Vector and Array Processors), MIMD, VLIW, Data Flow.
Lab Assignment 4 due, December 3.
Problem Set 5 due, December 3.December 10: Final Exam. 7 to 10pm.