EE 360N, Fall 1999
Y. N. Patt, Instructor
Francis Tseng, Seema Prasad, TAs
Lab Assignment 4; Due December 3, 1999

Introduction

The goal of this lab assignment is to extend the LC-2 simulator from lab 3 to handle virtual memory. You will augment the existing LC-2 microarchitecture with facilities for virtual to physical address translation.

The LC-2 virtual address space will have 16 pages, each of size 4K words. Physical memory will have 4 frames. Frame 0 is reserved for the operating system, and will not be used for this lab. Frame 1 holds additional system facilities, i.e. the interrupt handling code, exception handling code, and the page table. Frames 2 and 3 are available for swapping virtual pages. In addition, there are two modes of operation: kernel and user. Pages 0 and 1 cannot be accessed unless the LC-2 is in kernel mode. Since user programs operate in user mode, they cannot access those pages. Thus the user virtual memory space is 14 pages (pages 2-15).

The input to this new simulator will be:

1. A file entitled ucode which holds the expanded microcontrol store.
2. A file holding an LC-2 program that gets loaded into memory frame 1 (x1000).

This will be the interrupt service routine.
3. A file holding an LC-2 program that gets loaded into a different address in frame 1 (x1100).

This will be the exception handler followed by the page table.
4. A file holding another LC-2 program that gets loaded into memory frame 2 (x2000).
5. A file holding data for the program in frame 2. This data will be loaded into frame 3 (x3000).

Specifications

The Page Table

The page table should be placed in frame 1 of physical memory, between the code for the exception handler and space reserved for the stack. Note: it would be a good idea to place the page table directly under the exception handler in order to leave as much room as possible for the stack. A page table entry (PTE) contains only 6 bits of information, but for convenience, it is represented in a full 16 bit word. Thus one page table entry occupies one memory location. The format of each page table entry is as follows:

PFN = PTE[13:12], the page frame number

P = PTE[3], the protection bit
P=0 -> page can only be accessed in kernel mode
P=1 -> user has full rights to the page

V = PTE[2], the valid bit (V=1 for a valid page)

M = PTE[1], the modified bit (M=1 if page has been written)

R = PTE[0], the reference bit
R=1 -> page has been referenced since last timer interrupt
R=0 -> otherwise

All other bits are set to zero.

During the execution of instructions, your microcode will have to convert virtual addresses to physical addresses, as well as modify PTE's when necessary. To make address translation possible, we have added more structures to the datapath. We have added several registers: Page Table Base Register (PTBR) and Virtual Address Register (VA). The PTBR points to the first entry of the page table in physical memory. It's used to access a particular PTE during translation. To read from this register onto the bus, you should assert the GATE_PTBR signal. The VA register is basically a temporary register to hold the current address under translation. To read the VA register onto the bus and to write to the VA register from the bus, you should assert the GATE_VA and LD_VA control signals respectively. There is also a flipflop which holds the current mode of the machine. Two registers called 1 and 3 provide constants needed for modifying PTE's.

Interrupts and Exceptions

You'll have to modify the interrupt and RTI microcode only slightly. When vectoring to the ISR, the mode of the LC-2 should be switched to kernel. Likewise, upon RTI to the user program, the machine goes back to user mode. The timer interrupt service routine implemented in lab 3 must be modified for this lab. Instead of incrementing a counter, the interrupt will clear the reference bits for each entry of the page table, thus enabling a limited LRU replacement scheme for the operating system. Note: the timer will go off only once during program execution - during the 500th cycle.

Two classes of exceptions will exist in your extended LC-2. The first class is protection exception. Protection exceptions occur only when the machine is in user mode, and a memory page whose PTE protection bit is set to 0 is accessed. The mode of the LC-2 should be switched to kernel when handling exceptions. The second class of exception is page fault. For either class of exception, the PC is decremented and the machine is halted. On a real machine, of course, page faults will not cause the machine to halt, but rather will cause the current state to be saved and the PC to be loaded with a vector to the operating system's page fault handler. For our purposes, however, it will suffice to decrement the PC and halt.

Translating Addresses

Assume that at the beginning of each address translation phase that the virtual address is located in the MAR, and if the operation is a write, a source register holds the data to be written. Address translation consists of the following steps:

• Save the MAR into a temporary register VA

 
• Load the MAR with the address of the PTE of the current table
MAR[15:4] <- PTBR[15:4]
MAR[3:0] <- VA[15:12]
 
• Read the PTE of the current table into the MDR

 
• Check for a protection exception

 
• Check for a page fault

 
• Set the R bit

 
• If the pending instruction is a write, set the M bit

 
• Write the PTE back to memory

 
• Load the physical address into the MAR
MAR[13:12] <- PFN
MAR[11:0] <- VA[11:0]
 
• If the operation is a write, load the MDR with the source register

What to do for Lab 4

The following extensions must be made to your LC-2 simulator system:

Datapath
There are some minor modifications that need to be made to the datapath. i.e. How you take care of loading values into the MAR
during the translation process. Try to avoid doubling to 128 states.

Microsequencer
You'll need to add logic to detect page faults and protection exceptions. The state diagram must be altered so that any path into a state which uses memory now goes into a microcode routine that does address translation before using the memory. Hint: You will want to implement a micro-subroutine of sorts. The microsequencer must be extended to provide the necessary flow of control.

Microcode
Extra fields for the current LC-2 microinstructions will be required to control the address translation logic (e.g. LD_VA, GATE_VA) and provide control for the microsubroutine and processor mode. In addition, new microcode to do the virtual to physical address translation must be written. A key issue for this lab is when and where to call the address translation routine. With a little thought and planning, you'll avoid having to translate the virtual address on every memory access.

Writing Code
The interrupt service routine must traverse the entire page table, clearing the R bits of each PTE. You may assume when writing this code that the start address of the page table is fixed.
The user program in page 2 should do the following: sum the first 20 values stored in the memory locations beginning with xC000 (notice this is on page 12). This sum should then be stored at xC014. Then the program should jump to the address pointed to by this sum. Page 12 contains data to be used by the program on page 2. The following numbers should be stored there:
x0012, x0011, x2F39, x1023, x1002, x00F6, x0912, x0123, x0456, x0789, x0ABC, x0DEF, x0000, x0001, x0002, x0003, x0004, x0005, x0006, x0007.
These should be loaded into physical frame 3 on initialization of the simulator.

Initial Page Table Contents

The page table will be initialized upon simulator start-up. It should look as follows:

Page 0 is in frame 0. It is valid and unaccessible by the user.
Page 1 is in frame 1. It is valid and unaccessible by the user.
Page 2 is in frame 2. It is valid and accessible by the user.
Page 12 is in frame 3. It is valid and accessible by the user.
All other pages are invalid.

1. Adequately documented source code of your simulator called lc2sim.c.
2. The assembly code for the interrupt service routine, the exception handler, the page 2 program, and the page 3 data, called int.asm, except.asm, add.asm, and data.asm respectively.
3. The machine code for the interrupt service routine, the exception handler, the page 2 program, and the page 3 data, called int.hex, except.hex, and add.hex, and data.hex respectively.
4. The new microcode called ucode.
5. A file called dumpsim. To generate this file, simulate the LC-2 assembly programs by following the instructions in the next section.
6. A text file called readme that explains how you implemented this lab assignment. Describe any new fields you added to the microcode. What changes did you make to the datapath? Include a picture similar to the state machine that shows the new states you added(only show your changes). Describe what occurs at each state. Draw a logic diagram of your new microsequencer.

Things To Consider

The stack pointer and the PTBR will both contain physical addresses. The only time you need to update the reference/modified bits for the page 1 PTE is during the interrupt service routine. That is, you only need to update R or M within the context of an address translation for the page 1 PTE.

How will you design the kernel/user mode indicator so that interrupts are allowed to occur during interrupts? In other words, how do you really know when to switch back to user mode after servicing an interrupt?

How will you return from the address translation to the correct state? An obvious solution would be to have a register which holds the 6-bit return address. A better solution uses a multi-way branch from the final state of the address translation subroutine. You can use COND and the IR register to implement this branch.