Code for Dynamic Insertion Policy (DIP)
(Works on Linux.  Known to not work on Sun machines with Unix)


Download: 
To  execute the sample code, download the following files:

  1. mcache.h => The header file for the simulated cache
  2. mcache.c => The source file for the simulated cache
  3. cachesim.c => A cache simulator that contains the trace reader
  4. Makefile => A sample makefile
  5. art_00.atr.gz => A trace file containing the L2 access stream for the art benchmark (57 MB)
  6. ammp_00.atr.gz => A trace file containing the L2 access stream for the art benchmark (21 MB)

Compile:
After saving these files in a directory, compile the code by typing "make". This should produce the executable cachesim.
Type ./cachesim -h for help.


Sample runs:

For testing cachesim for the art benchmark, type "make test_art".  This should simulate four cache configurations:

1.   The baseline 1MB 16-way LRU-managed cache
./cachesim  art_00.atr.gz
=======================
Count: 12659457
Miss:  9684536 (76.50%)
MPKI: 38.74
=======================

2.   A 1 MB 16-way cache with LRU Insertion Policy (LIP)
./cachesim -bip_epsilon 0 art_00.atr.gz
=======================
Count: 12659457
Miss:  5893373 (46.55%)
MPKI: 23.57
=======================

3.   A 1 MB 16-way cache with Bimodal Insertion Policy (BIP) which inserts in the MRU position once every 32 misses  (1/32 = 0.0325)
./cachesim -bip_epsilon 0.0325  art_00.atr.gz
=======================
Count: 12659457
Miss:  4491564 (35.48%)
MPKI: 17.97
=======================

4.  A 1MB 16-way cache with Dynamic Insertion Policy (DIP) to choose between BIP and LRU using 32 dedicated sets to each policy
./cachesim -bip_epsilon 0.0325 -dip 32   art_00.atr.gz
=======================
Count: 12659457
Miss:  4510906 (35.63%)
MPKI: 18.04
=======================

For testing cachesim for the armmp benchmark, type "make test_ammp".  This should also simulate four cache configurations:

1.   The baseline 1MB 16-way LRU-managed cache
./cachesim  ammp_00.atr.gz
=======================
Count: 3738142
Miss:   708712 (18.96%)
MPKI: 2.83
=======================

2.   A 1 MB 16-way cache with LRU Insertion Policy (LIP)
./cachesim -bip_epsilon 0 ammp_00.atr.gz
=======================
Count: 3738142
Miss:  1011653 (27.06%)
MPKI: 4.05
=======================

3.   A 1 MB 16-way cache with Bimodal Insertion Policy (BIP) which inserts in the MRU position once every 32 misses  (1/32 = 0.0325)
./cachesim -bip_epsilon 0.0325  ammp_00.atr.gz
=======================
Count: 3738142
Miss:   737974 (19.74%)
MPKI: 2.95
=======================

4.  A 1MB 16-way cache with Dynamic Insertion Policy (DIP) to choose between BIP and LRU using 32 dedicated sets to each policy
./cachesim -bip_epsilon 0.0325 -dip 32   ammp_00.atr.gz
=======================
Count: 3738142
Miss:   552930 (14.79%)
MPKI: 2.21
=======================

For ammp, DIP outperforms the component policies (LRU and BIP) because it dynamically selects the policy best suited to paritcular phase of the program. 


Generating the trace file:
The trace for the art and ammp benchmarks was obtained by using a single simpoint of 250M instructions.  The first-level I and D caches is configured as 16kB, 2-way with 64B linesize. Each entry in the trace.atr file contains 20B where the first 4B is the instruction sequence number in the 250M instructions, the next 8B represents the instruction address that generated the L2 access request, and the last 8B represents the virtual address of the data requested from the L2.  The trace.atr file is compressed using gzip and the resulting trace.atr.gz file is used as the input to cachesim.


Disclaimer:
Standard open-source policies apply. 

Please feel free to email me if you have any questions, comments, suggestions, or feedback.

This document was generated by Moinuddin on May 1, 2007