Digital Systems Design Using VHDL

Links to an  up-to-date errata list and slides for all chapters are provided on this page in pdf format.  You will need Acrobat Reader 3.0 (or later) to view these documents.  You can download the slides and print them out to make transparencies.  If you have an LCD projector for your computer, you can download the slides and use Acrobat Reader in the full screen mode as a slide viewer.

All of the VHDL code in the textbook (including corrections) is available on the Brooks/Cole web site:

Software Requirements for Digital Systems Design Using VHDL

In order to use this book effectively, students need to have access to appropriate VHDL software for compiling, simulating, and synthesizing VHDL code.  The VHDL software should preferably implement the complete IEEE-1993 VHDL Standard.  All of the examples in the book have been tested using software that conforms to this standard.  Some manufacturers of FPGAs and CPLDs provide software that only implements a subset of VHDL, and many of the examples in this book will have to be modified before they can be compiled and simulated using such software.  Some software only implements a synthesizable subset of the VHDL code, and delays are not implemented.  It would not be possible to do some of the timing simulations in the book using such software.

We are currently using the Aldec Active-VHDL software, which implements the full IEEE standard, for compilation and simulation of VHDL code.  We use the XILINX  Foundation Express for synthesis and implementation using FPGAs.  The latter software also provides for schematic entry and simulation.  All of the examples in the text have been tested using the Aldec Active-VHDL software.  The synthesis examples have been tested using the XILINX Foundation Express along with XILINX demo boards.  Some synthesis examples have also been tested using the Altera MAX+PLUS II software along with Altera education boards.  However, for the Altera software, VHDL code that implies internal tri-state busses must be changed to imply multiplexers.

Most CAD software vendors have University programs and will supply VHDL software at relatively low cost to universities.  Some manufacturers of FPGAs and CPLDs can also supply hardware boards for testing at relatively low cost.  Information about University Educational programs can usually be obtained on web sites, and in some cases you can download an evaluation copy of the software.

For Aldec Active-VHDL:

For XILINX software and hardware:

For Altera software and hardware:

Using VHDL Libraries

 Many of the examples in Chapters 2 through 7 use a library called Bitlib.  In order to compile these examples, you must first compile the Bitpack.vhd source file and then create the Bitlib.  The method used to create a library depends on the software that you are using.  Most of the examples in Chapters 8 through 11 make use of IEEE standard libraries or variations thereof.

 The IEEE standards provide several packages for synthesis including ieee.std_logic_1164,  ieee.numeric_bit, and ieee.numeric_std.  The latter two contain definitions of signed and unsigned types together with overloaded arithmetic, comparison, logic, and conversion functions for working with these types.  Unfortunately, some CAD vendors have not adopted these standard libraries.

 Synopsis, one of the major CAD vendors, uses its own set of libraries: ieee.std_logic_arith, ieee.std_logic_signed, and ieee.std_logic_unsigned.  These libraries have been adopted by a number of other CAD vendors.  The Aldec Active-VHDL has both the IEEE standard libraries and the Synopsis libraries.  At this writing, the XILINX Foundation Express contains has the Synopsis libraries, but it does not have the ieee.numeric_bit or ieee.numeric_std packages.  If these numeric packages are not available, two options for implementing arithmetic functions are:

(1)  Use signed or unsigned vectors along with the following libraries:
     library ieee;
     use ieee.std_logic_1164.all
     use ieee.std_logic_arith.all
This combination provides definitions of signed and unsigned types, and overloading functions for addition, subtraction, multiplication, and comparison for signed and unsigned types along with conversion functions.  But it does not contain overloading functions for AND, OR, NOT, and other common logic operators. If you choose to write your code using this method, you can still do logic operations on a bit-by-bit basis.

(2)  Do not use signed or unsigned types.  Use type std_logic_vector instead.  Then use the following libraries:
     library ieee;
     use ieee.std_logic_1164.all
     use ieee.std_logic_arith.all
     use ieee.std_logic_unsigned.all  (or ieee.std_logic_signed.all)
The last package provides overloading arithmetic and comparison functions for std_logic_vectors, and these functions treat the std_logic_vectors the same as if they were unsigned (or signed) type.  Since the ieee.std_logic_1164 package contains the overloading logic functions, you then have everything you need.

Using Aldec Active-HDL version 3.5 Student Edition

 The  Student Edition of Aldec Active-HDL version 3.5 is now available and can be ordered from the Aldec web page: for $49.95 including a Quick Start Guide.  This software has several limitations including restrictions on file sizes and design names, but it is a full implementation of the IEEE standard VHDL and it has a very friendly user interface.  The Aldec Active-HDL Student Edition is also available packaged with Digital Systems Design Using VHDL from Brooks/Cole.

 All of the examples in the book should compile and simulate correctly using Active-HDL version 3.5 Student Edition, with the exception of the 6805 microcontoller example in Appendices D and E.  The size of these examples exceeds the limits of the Student Edition.  The Student Edition should be adequate for almost all of the homework problems in the book, but larger projects may require the Standard Edition.

 After you have installed the Active-HDL Student Edition on your computer, you should install the bit library that is used in many examples in the text.  First, download Bit_pack.vhd from the Brooks/Cole web site.  Then proceed as follows:
1.  Open Active-HDL SE.
     If you have already created a design, open that design and go to step 4; otherwise choose "Create new design" and proceed to step 2.
2.  Type the design name:  design1  (click next).
3.  Select "Create an empty design" (click next, then click finish)
4.  Select "Create library" on the Design menu.
5.  Type the name of the library:  design0
    Note: you cannot use the name "bitlib" because of the limitations of the student edition.
6.  Select the location of the library files:  C:\...\aldec\vlib    (Specify the path to vlib; your library must be placed in vlib with the other libraries.)
7.  Click next, then click Add Files.
8.  Locate and select the Bit_pack.vhd file that you downloaded..
9.  Click add, then next, then finish.  After compilation is complete, you should get a message that design0.LIB was successfully created.

For any of the examples in the book that use bitlib, replace "bitlib" with "design0" before compiling.  If you want to use Mvllib, you will have to create a separate library for Mvllib using the procedures described above.