Nur A. Touba - Presentations

• "Efficient Linear Decompression Using ATE Vector Repeat-Per-All-Pins" IEEE International Test Synthesis Workshop, Mar. 2009.

• "Selecting Signals to Observe for Silicon Debug" IEEE International Test Synthesis Workshop, Mar. 2009.

• "Improving Memory Repair by Selective Row Partitioning" IEEE International Test Synthesis Workshop, Mar. 2009.

• "DFT Test Time Reduction", Southwest DFT Workshop, Apr. 2008.

• "Using an X-Canceling MISR with Deterministic Observation for Increasing Output Compaction in the Presence of Unknowns", IEEE International Test Synthesis Workshop, Apr. 2008.

• "Expanding Observation Window for Trace Buffer via Selective Data Capture", IEEE International Test Synthesis Workshop, Apr. 2008.

• "X-Canceling - A Way to Compact Output Responses with X's Using a MISR," IEEE North Atlantic Test Workshop, May 2007.

• "A Low Cost Code-Based Methodology for Tolerating Multiple Bit Upsets in Memories," IEEE Workshop on System Effects of Logic Soft Errors, Apr. 2007.

• "How to Compact Output Reponses with X's Using a MISR without Losing Fault Coverage via Symbolic Simulation", IEEE International Test Synthesis Workshop, Mar. 2007.

• "Using Limited Dependence Sequential Expansion for Decompressing Test Vectors," IEEE North Atlantic Test Workshop, May 2006.

• "Using Rectangular Coding to Combine Linear and Non-Linear Test Vector Compression", IEEE International Test Synthesis Workshop, Apr. 2006.

• "Test Vector Compression Based on Limited Depth Sequential Expansion", IEEE BAST Workshop, Feb. 2006.

• "Low Power BIST Based on Scan Chain Partitioning", IEEE International Test Synthesis Workshop, Apr. 2005.

• "SLING: A Procedure for Synthesis of Linear Test Pattern Generators with Strong Randomness Properties", IEEE International Test Synthesis Workshop, Apr. 2005.

• "Exploiting Asymmetrical Soft Error Susceptibility for Cost-effective Concurrent Error Detection in Logic Circuits", IEEE Workshop on System Effects of Logic Soft Errors, Apr. 2005.

• "Compressing Functional Tests for Microprocessors", IEEE International Workshop on Microprocessor Test and Verification, Sep. 2004.

• "Entropy Limits on Test Data Compression", IEEE International Test Synthesis Workshop, Apr. 2004.

• "Low Power LFSR Reseeding", IEEE International Test Synthesis Workshop, Apr. 2004.

• "Using an Embedded Processor for Diagnostic Response Compaction", IEEE International Workshop on Microprocessor Test and Verification, Jun. 2003.

• "A Variable Length Continuous-Flow Scan Vector Decompression Scheme", IEEE European Test Workshop, May 2003.

• "Non-Deterministic Behavior in the Test of High-Speed Packet Switched I/O Ports", IEEE International Test Synthesis Workshop, Apr. 2003.

• "Deterministic Test Vector Decompression in Software Using Linear Operations", IEEE International Test Synthesis Workshop, Apr. 2003.

• "Multi-Phase Shifting to Reduce Instantaneous Peak Power during Scan", IEEE Latin-American Test Workshop, Feb. 2003.

• "Matrix-Based Test Vector Decompression Using an Embedded Processor", IEEE International Workshop on Microprocessor Test and Verification, Jun. 2002.

• "Improving Test Data Compression Based on LFSR Reseeding", IEEE International Test Synthesis Workshop, Mar. 2002.

• "Reducing Peak Power Consumption During Scan Testing by Vector Modification", IEEE International Test Synthesis Workshop, Mar. 2002.

• "Very Low Voltage Testing of SOI Integrated Circuits", IEEE Latin-American Test Workshop, Feb. 2002.

• "Reducing Test Power Using Programmable Scan Chain Disable", IEEE International Workshop on Electronic Design, Test, and Applications, Jan. 2002.

• "Reducing Test Data Volume for Cores Using Dynamic LFSR Reseeding", IEEE International Workshop on Testing Embedded Core-based Systems, May 2001.

• "Disabling Scan Chains to Reduce Power Dissipation During Test", IEEE International Test Synthesis Workshop, Mar. 2001.

• "Weighted Pseudo-Random Hybrid BIST" IEEE International Test Synthesis Workshop, Mar. 2001.

• "Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes", IEEE On-Line Test Workshop, Jul. 2000.

• "Static Compaction Techniques to Control Scan Vector Power Dissipation", IEEE International Test Synthesis Workshop, Mar. 2000.

• "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns", IEEE International Test Synthesis Workshop, Mar. 2000.

• "Scan Length Reduction in Cores Using Virtual Scan Chains", IEEE International Workshop on Testing Embedded Core-based Systems, Apr. 1999.

• "Fault Diagnosis in Scan-Based BIST Using both Time and Space Information", IEEE International Test Synthesis Workshop, Mar. 1999.

• "Efficient Testing of Systems-on-a-Chip Using an Embedded Processor", IEEE International Test Synthesis Workshop, Mar. 1999.

• "Test Vector Compression/Decompression for Systems-on-a-Chip Using Statistical Coding", IEEE High-Level Design, Validation, and Test Workshop, Nov. 1998.

• "Test Data Compression/Decompression Schemes for Testing Core-Based Designs", IEEE International Test Synthesis Workshop, Mar. 1998.

• "Synthesizing Circuits with High Fault Coverage for a Specified BIST Environment", IEEE International Test Synthesis Workshop, Mar. 1998.

• "Space Compaction in Core-Based Designs", IEEE High-Level Design, Validation, and Test Workshop, Nov. 1997.

• "Modifying User-Defined Logic to Provide Test Access to Embedded Cores", IEEE International Test Synthesis Workshop, May 1997.

• "Special ATPG for Correlating Test Patterns for Low-Overhead Mixed-Mode BIST", IEEE International Test Synthesis Workshop, May 1997.

• "Partial Isolation Rings for Testing Embedded Cores", IEEE High-Level Design, Validation, and Test Workshop, Nov. 1996.

• "Altering a Pseudo-Random Bit Sequence for Mixed-Mode Scan BIST", IEEE International Test Synthesis Workshop, May 1996.

• "Test Point Insertion Based on Path Tracing", IEEE BAST Workshop, Feb. 1996.

• "Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST", IEEE International Test Synthesis Workshop, May 1995.

• "Transformed Pseudo-Random Patterns for BIST", IEEE Built-In Self-Test / Design-For-Testability Workshop, Mar. 1995.

• "Synthesis of Mapping Logic", IEEE BAST Workshop, Feb. 1995.

• "Logic Synthesis of Random Pattern Testable Circuits Using Algebraic Transformations," IEEE International Test Synthesis Workshop, May. 1994.

• "Synthesis of Random Pattern Testable Circuits", IEEE BAST Workshop, Feb. 1994.

• "Improving Scan Vector Compression Based on Linear Decompressors" Intel, Austin, TX, Feb. 2003.

• "Techniques for Reducing Test Data Volume" Synopsys, Sunnyvale, CA, Apr. 2002.

• "Dynamic LFSR Reseeding: A Simple and Highly Efficient Test Vector Encoding Scheme", Intel, Austin, TX, Aug. 2001.

• "Dynamic LFSR Reseeding", University of Stuttgart, Stuttgart, Germany, Mar. 2001.

• "Methodology for Internal Error Detection", Hewlett Packard, Richardson, TX, Feb. 2001.

• "Improving Delay Fault Diagnosis in FPGA's", Stanford CAD Day, Stanford, CA, Nov. 2000.

• "Combining External Testing and BIST", Intel Test Research Symposium, Santa Clara, CA, Oct. 2000.

• "Virtual Scan Chains: A Means for Reducing Scan Length in Cores", Stanford CAD Day, Stanford, CA, Nov. 1999.

• "Current Research in System-on-a-Chip Testing and Diagnosis", Fujitsu Labs, Santa Clara, CA, Jul. 1999.

• "Current Research in System-on-a-Chip Testing and Diagnosis", Intel, Santa Clara, CA, Jul. 1999.

• "Overview of Current Research in Testing and Diagnosis" Synopsys, Sunnyvale, CA, Jul. 1999.

• "Test Data Compression/Decompression Using Cyclical Scan Chains", Jadavpur Univserity, Calcutta, India, Jan. 1999.

• "New Techniques for Delay Fault Diagnosis", Stanford CAD Day, Stanford, CA, Nov. 1998.

• "Scan Vector Compression for Systems-on-a-Chip", SynTest, Sunnyvale, CA, Jul. 1998.

• "Observing Test Response of Embedded Cores", Stanford CAD Day, Stanford, CA, Nov. 1997.

• "Overview of Current Research in Core Testing", Duet Technologies, San Jose, CA, Nov. 1997.

• "Overview of Current Research", Tandem Computer, Austin, TX, Oct. 1997.

• "Providing Test Access to Embedded Cores", University of Southern California (USC), Los Angeles, CA, Aug. 1997.

• "Obtaining High Fault Coverage with Circular BIST Via State Skipping", University of Trondheim, Trondheim, Norway, Jun. 1997.

• "Partial Isolation Rings for Testing Embedded Cores", Cirrus Logic, San Jose, CA, Feb. 1997.

• "Partial Isolation Rings for Testing Embedded Cores", Fujitsu, Milpitas, CA, Feb. 1997.

• "Overview of Current Research and Future Plans", IBM Austin Research Lab, Austin, TX, Nov. 1996.

• "Overview of Current Research and Future Plans", Advanced Micro Devices (AMD), Milpitas, CA, Nov. 1996.

• "Overview of Current Research and Future Plans", Synopsis, Mountain View, CA, Nov. 1996.

• "Circular BIST with State-Skipping", Stanford CAD Day, Stanford, CA, Nov. 1996.

• "Synthesis Techniques for Pseudo-Random BIST", DARPA Embedded Systems PI Meeting, San Deigo, CA, Jun. 1996.

• "Altering a Pseudo-Random Sequence of Bits for Scan-Based BIST", LogicVision BIST Forum, Princeton, NJ, May 1996.

• "Synthesis Techniques for Pseudo-Random BIST", Texas A&M University, College Station, TX, Mar. 1996.

• "Test Point Insertion Based on Path Tracing", Stanford CAD Day, Stanford, CA, Nov. 1995.

• "Synthesis of Mapping Logic" Compass Design Automation, San Jose, CA, Jun. 1995.

• "Synthesis of Mapping Logic" Stanford CAD Day, Stanford, CA, Nov. 1994.

• "Logic Synthesis for Concurrent Error Detection" Stanford CAD Day, Stanford, CA, Nov. 1993.