Nur A. Touba - Publications

• K.J. Balakrishnan and N.A. Touba, "Relationship Between Entropy and Test Data Compression", IEEE Transactions on Computer-Aided Design, Vol. 23, No. 4, pp. 386-395, Feb. 2007.

• J. Lee and N.A. Touba, "LFSR Reseeding Scheme Achieving Low Power Dissipation During Test", IEEE Transactions on Computer-Aided Design, Vol. 26, No. 2, pp. 396-401, Feb 2007.

• K.J. Balakrishnan and N.A. Touba, "Improving Linear Test Data Decompression", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 11, pp. 1227-1237, Nov. 2006.

• N.A. Touba, "Survey of Test Vector Compression Techniques", IEEE Design & Test Magazine, Vol. 23, Issue 4, pp. 294-303, Jul. 2006

• E. MacDonald and N.A. Touba, "Delay Testing of Partially Depleted Silicon-On-Insulator (PD-SOI) Circuits", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 6, pp. 587-595, Jun. 2006.

• S. Ghosh, S. Basu , and N.A. Touba, "Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits", Journal of Low Power Electronics, Vol. 1, No. 1, pp. 63-72, Apr. 2005.

• A. Jas, C.V. Krishna, and N.A. Touba, "Weighted Pseudo-Random Hybrid BIST", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 12, pp. 1277-1283, Dec. 2004.

• K. Mohanram and N.A. Touba, "Lowering Power Consumption in Concurrent Checkers via Input Ordering", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 11, pp. 1234-1243, Nov. 2004.

• C.V Krishna, A. Jas, and N.A. Touba, "Achieving High Encoding Efficiency with Partial Dynamic Reseeding", ACM Transactions on Design Automation of Electronic Systems, Vol. 9, Issue 4, pp. 500-516, Oct. 2004.

• A. Jas, B. Pouya, and N.A. Touba, "Test Data Compression Technique for Embedded Cores Using Virtual Scan Chains", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 7, pp. 775-780, Jul. 2004.

• K.J. Balakrishnan and N.A. Touba, "Matrix-Based Software Test Data Decompression for Systems-on-a-Chip", Journal of Systems Architecture, Vol. 50, Issue 5, pp. 247-256, Apr. 2004.

• L. Li, K. Chakrabarty, and N.A. Touba, "Test Data Compression using Dictionaries with Selective Entries and Fixed-Length Indices", ACM Transactions on Design Automation of Electronic Systems, Vol. 8, Issue 4, pp. 470-490, Oct. 2003.

• A. Jas, J. Ghosh-Dastidar, M.-E. Eng, and N.A. Touba, "An Efficient Test Vector Compression Scheme Using Selective Huffman Coding", IEEE Transactions on Computer-Aided Design, Vol. 22, No. 6, pp. 797-806, Jun. 2003.

• N.A. Touba, "Circular BIST With State Skipping", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 5, pp. 668-672, Oct. 2002.

• A. Jas and N.A. Touba, "Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor", Journal on Electronic Testing: Theory and Applications (JETTA), Vol. 18, Issue 4/5, pp. 503-514, Aug. 2002.

• N.A. Touba and E.J. McCluskey, "Bit-Fixing in Pseudo-Random Sequences for Scan BIST", IEEE Transactions on Computer-Aided Design, Vol. 20, No. 4, pp. 545-555, Apr. 2001.

• N.A. Touba and E.J. McCluskey, "RP-SYN: Synthesis of Random-Pattern Testable Circuits with Test Point Insertion", IEEE Transactions on Computer-Aided Design, Vol. 18, No. 8, pp. 1202-1213, Aug. 1999.

• D. Das and N.A. Touba, "Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes", Journal on Electronic Testing: Theory and Applications (JETTA), Vol. 15, Issue 1/2, pp. 145-155, Aug. 1999.

• N.A. Touba and E.J. McCluskey, "Logic Synthesis of Multilevel Circuits with Concurrent Error Detection", IEEE Transactions on Computer-Aided Design, Vol. 16, No. 7, pp. 783-789, Jul. 1997.

• N.A. Touba and B. Pouya, "Using Partial Isolation Rings to Test Core-Based Designs", IEEE Design & Test Magazine, Vol. 14, Issue 4, pp. 52-59, Oct. 1997.

2009

• J.-S. Yang, N.A. Touba, and B. Nadeau-Dostie, "Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points", Proc. of IEEE International Test Conference, 2009.

• J.-S. Yang, N.A. Touba, S.-Y. Yang, and T.M. Mak, "Industrial Case Study for X-Canceling MISR", Proc. of IEEE International Test Conference, 2009.

• J.-S. Yang, B. Nadeau-Dostie, and N.A. Touba, "Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points", Proc. of IEEE Symposium on Defect and Fault Tolerance, 2009.

• M. Rab, A. Bawa, and N.A. Touba, "Improving Memory Repair by Selective Row Partitioning", Proc. of IEEE Symposium on Defect and Fault Tolerance, 2009.

• J.-S. Yang and N.A. Touba, "Automated Selection of Signals to Observe for Efficient Silicon Debug" Proc. of IEEE VLSI Test Symposium, pp. 79-84, 2009.

• R. Datta and N.A. Touba, "Exploiting Unused Spare Columns to Improve Memory ECC" Proc. of IEEE VLSI Test Symposium, pp. 47-52, 2009.

  2008

• J.-S. Yang and N.A. Touba, "Enhancing Silicon Debug via Periodic Monitoring", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 125-133, 2008. (Received Best Paper Award)

• R. Garg, R. Putman, and N.A. Touba "Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation", Proc. of IEEE VLSI Test Symposium, pp. 35-42, 2008.

• J.-S. Yang and N.A. Touba "Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture", Proc. of IEEE VLSI Test Symposium, pp. 345-351, 2008.

  2007

• N.A. Touba, "X-Canceling MISR - An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR", Proc. of IEEE International Test Conference, Paper 6.2, 2007. (Listed among top ten best papers)

• A. Dutta and N.A. Touba, "Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 3-11, 2007.

• A. Dutta and N.A. Touba "Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code", Proc. of IEEE VLSI Test Symposium, pp. 349-354, 2007.

• R. Putman and N.A. Touba, "Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression", Proc. of IEEE VLSI Test Symposium, pp. 211-216, 2007.

  2006

• A. Dutta and N.A. Touba, "Using Limited Dependence Sequential Expansion for Decompressing Test Vectors", Proc. of IEEE International Test Conference, Paper 23.1, 2006.

• J. Lee and N.A. Touba, "Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition", Proc. of IEEE Asian Test Symposium, pp. 237-244, 2006.

• A. Dutta and N.A. Touba, "Synthesis of Efficient Linear Test Pattern Generators", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 206-214, 2006.

• J. Lee and N.A. Touba, "Combining Linear and Nonlinear Test Vector Compression Using Correlation-Based Rectangular Encoding", Proc. of IEEE VLSI Test Symposium, pp. 252-257, 2006.

• A. Dutta and N.A. Touba "Iterative OPDD Based Signal Probability Calculation", Proc. of IEEE VLSI Test Symposium, pp. 72-77, 2006.

  2005

• K.J. Balakrishnan, N.A. Touba, S. Patil, "Compressing Functional Tests for Microprocessors", Proc. of IEEE Asian Test Symposium, pp. 428-433, 2005.

• A. Dutta and N.A. Touba "Synthesis of Non-Intrusive Concurrent Error Detection Using an Even Error Detecting Function", Proc. of IEEE International Test Conference, pp. 1059-1066, 2005.

• S.I. Ward, C. Schattauer, and N.A. Touba, "Using Statistical Transformations to Improve Compression for Linear Decompressors", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 42-50, 2005.

• J. Lee and N.A. Touba, "Low Power BIST Based on Scan Partitioning", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 33-41, 2005.

• A. Dutta, T. Rodrigues, and N.A. Touba, "Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier", Proc. of IEEE Annual Symposium on VLSI, pp. 200-205, Vol. 2, 2005.

• S. Ghosh, S. Basu, and N.A. Touba, "Synthesis of Low Power CED Circuits based on Parity Codes", Proc. of IEEE VLSI Test Symposium, pp. 315-320, 2005.

• K.J. Balakrishnan and N.A. Touba, "Reconfigurable Linear Decompressors using Symbolic Gaussian Elimination", Proc. of IEEE Design, Automation and Test in Europe, pp. 1130-1135, Vol. 2, 2005.

  2004

• K.J. Balakrishnan and N.A. Touba, "Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion", Proc. of IEEE International Test Conference, pp. 936-943, 2004.

• S. Ghosh, S. Basu, and N.A. Touba, "Reducing Power Consumption in Memory ECC Checkers", Proc. of IEEE International Test Conference, pp. 1322-1331, 2004.

• J. Lee and N.A. Touba, "Low Power Test Data Compression Based on LFSR Reseeding", Proc. of IEEE International Conference on Computer Design, pp. 180-185, 2004.

• K.J. Balakrishnan and N.A. Touba, "Relating Entropy Theory to Test Data Compression", Proc. of IEEE European Test Symposium, pp. 94-99, 2004.

• S. Ghosh, E. MacDonald, S. Basu, and N. A. Touba, "Low-Power Weighted Pseudo-Random BIST Using Special Scan Cells", Proc. of the ACM Great Lakes Symposium on VLSI, pp. 86-91, 2004.

• C.V. Krishna and N.A. Touba, "3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme", Proc. of IEEE VLSI Test Symposium, pp. 79-86, 2004.

  2003

• C.V. Krishna and N.A. Touba, "Adjustable Width Linear Combinational Scan Vector Decompression", Proc. of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 863-866, 2003.

• K. Mohanram and N.A. Touba, "Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 433-440, 2003.

• K.J. Balakrishnan and N.A. Touba, "Scan-Based BIST Diagnosis Using an Embedded Processor", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 209-216, 2003.

• C.V. Krishna and N.A. Touba, "Hybrid BIST Using an Incrementally Guided LFSR", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 217-224, 2003.

• K. Mohanram and N.A. Touba, "Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits", Proc. of IEEE International Test Conference, pp. 893-901, 2003.

• K. Mohanram, E.S. Sogomonyan, M. Goessel, and N.A. Touba, "Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits", Proc. of International On-Line Test Symposium, pp. 35-40, 2003.

• K.J. Balakrishnan and N.A. Touba, "Deterministic Test Vector Decompression in Software Using Linear Operations", Proc. of IEEE VLSI Test Symposium, pp. 225-231, 2003.

• K. Mohanram and N.A. Touba, "Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses", Proc. of IEEE VLSI Test Symposium, pp. 121-127, 2003.

• S.Ghosh, S.Basu, and N.A. Touba, "Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering", Proc. of IEEE Symposium on VLSI, pp. 246-249, 2003.

  2002

• K. Mohanram and N.A. Touba, "Input Ordering in Concurrent Checkers to Reduce Power Consumption", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 87-95, 2002.

• K.J. Balakrishnan and N.A. Touba, "Matrix-Based Test Vector Decompression Using an Embedded Processor", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 159-165, 2002.

• R. Sankaralingam and N.A. Touba, "Inserting Test Points to Control Peak Power During Scan Testing", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 138-146, 2002.

• C.V. Krishna and N.A. Touba, "Reducing Test Data Volume Using LFSR Reseeding with Seed Compression", Proc. of IEEE International Test Conference, pp. 321-330, 2002.

• R. Sankaralingam and N.A. Touba, "Controlling Peak Power During Scan Testing", Proc. of IEEE VLSI Test Symposium, pp. 153-159, 2002.

• E. MacDonald and N.A. Touba, "Very Low Voltage Testing of SOI Integrated Circuits", Proc. of IEEE VLSI Test Symposium, pp. 25-30, 2002.

• K. Mohanram, C.V. Krishna, and N.A. Touba "A Methodology for Automated Insertion of Concurrent Error Detection Hardware in Synthesizable Verilog RTL", Proc. of IEEE International Symposium on Circuits and Systems, pp. 577-580, 2002.

  2001

• C.V. Krishna, A. Jas, and N.A. Touba, "Test Vector Encoding Using Partial LFSR Reseeding", Proc. of IEEE International Test Conference, pp. 885-893, 2001.

• J. Ghosh-Dastidar and N.A. Touba, "Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 215-220, 2001.

• A. Jas, C.V. Krishna, and N.A. Touba, "Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme", Proc. of IEEE VLSI Test Symposium, pp. 2-8, 2001. (Received Best Paper Award)

• R. Sankaralingam, B. Pouya, and N.A. Touba, "Reducing Power Dissipation During Test Using Scan Chain Disable", Proc. of IEEE VLSI Test Symposium, pp. 319-324, 2001.

  2000

• E. MacDonald and N.A. Touba, "Testing Domino Circuits in SOI Technology", Proc. of IEEE Asian Test Symposium, pp. 441-446, 2000.

• D. Das and N.A. Touba, "Reducing Test Data Volume Using External/LBIST Hybrid Test Patterns", Proc. of IEEE International Test Conference, pp. 115-122, 2000.

• J. Ghosh-Dastidar and N.A. Touba, "Diagnosing Resistive Bridges Using Adaptive Techniques", Proc. of IEEE Custom Integrated Circuits Conference, pp. 79-82, 2000.

• A. Jas, B. Pouya, and N.A. Touba, "Virtual Scan Chains: A Means for Reducing Scan Length in Cores", Proc. of IEEE VLSI Test Symposium, pp. 73-78, 2000.

• J. Ghosh-Dastidar and N.A. Touba, "A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains", Proc. of IEEE VLSI Test Symposium, pp. 79-85, 2000.

• R. Sankaralingam, R.R. Oruganti, and N.A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation", Proc. of IEEE VLSI Test Symposium, pp. 35-40, 2000.

  1999

• A. Jas, K. Mohanram and N.A. Touba, "An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets", Proc. of IEEE Asian Test Symposium, pp. 275-280, 1999.

• A. Jas and N.A. Touba, "Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip", Proc. of IEEE International Conference on Computer Design (ICCD), pp. 418-423, 1999.

• J. Ghosh-Dastidar, D. Das, and N.A. Touba, "Diagnosis in Scan-Based BIST Using Both Time and Space Information", Proc. of IEEE International Test Conference, pp. 95-102, 1999. (Received Best Student Paper Award)

• E. MacDonald and N.A. Touba, "Delay Testing of SOI Circuits: Challenges with the History Effect", Proc. of IEEE International Test Conference, pp. 269-275, 1999.

• A. Jas, J. Ghosh-Dastidar, and N.A. Touba, "Scan Vector Compression/Decompression Using Statistical Coding", Proc. of IEEE VLSI Test Symposium, pp. 114-120, 1999.

• J. Ghosh-Dastidar and N.A. Touba, "Adaptive Techniques for Improving Delay Fault Diagnosis", Proc. of IEEE VLSI Test Symposium, pp. 168-172, 1999.

• D. Das and N.A. Touba, "Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits", Proc. of IEEE VLSI Test Symposium, pp. 370-376, 1999.

• P.K. Jaini and N.A. Touba, "Observing Test Response of Embedded Cores through Surrounding Logic", Proc. of IEEE International Symposium on Circuits and Systems, pp. 119-123, 1999.

• W. Quddus, A. Jas, and N.A. Touba, "Configuration Self-Test in FPGA-Based Reconfigurable Systems", Proc. of IEEE International Symposium on Circuits and Systems, pp. 97-100, 1999.

• D. Das and N.A. Touba, "A Low Cost Approach for Detecting, Locating, and Avoiding Interconnet Faults in FPGA-Based Reconfigurable Systems", Proc. of IEEE International Conference on VLSI Design, pp. 266-269, 1999.

  1998

• M. Karkala, N.A. Touba, and H.-J. Wunderlich, "Special ATPG to Correlate Test Patterns for Low Overhead Mixed-Mode BIST", Proc. of IEEE Asian Test Symposium, pp. 492-499, 1998.

• J. Ghosh-Dastidar and N.A. Touba, "A Systematic Approach for Diagnosing Multiple Delay Faults", Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 211-216, 1998.

• A. Jas and N.A. Touba, "Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core-Based Designs", Proc. of IEEE International Test Conference, pp. 458-464, 1998.

• Z. Zhao, B. Pouya, and N.A. Touba, "BETSY: Synthesizing Circuits for a Specified BIST Environment", Proc. of IEEE International Test Conference, pp. 144-153, 1998.

• B. Pouya and N.A. Touba, "Synthesis of Zero-Aliasing Elementary-Tree Space Compactors", Proc. of IEEE VLSI Test Symposium, pp. 70-77, 1998.

• D. Das and N.A. Touba, "Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes", Proc. of IEEE VLSI Test Symposium, pp. 309-315, 1998.

  1997

• B. Pouya and N.A. Touba, "Modifying User-Defined Logic for Test Access to Embedded Cores", Proc. of IEEE International Test Conference, pp. 60-68, 1997.

• N.A. Touba and E.J. McCluskey, "Pseudo-Random Pattern Testing of Bridging Faults ", Proc. of IEEE International Conference on Computer Design (ICCD), pp. 54-60, 1997.

• N.A. Touba and B. Pouya, "Testing Embedded Cores Using Partial Isolation Rings", Proc. of IEEE VLSI Test Symposium, pp. 10-16, 1997.

• N.A. Touba, "Obtaining High Fault Coverage with Circular BIST Via State Skipping", Proc. of IEEE VLSI Test Symposium, pp. 410-415, 1997.

  1996

• N.A. Touba and E.J. McCluskey, "Altering a Pseudo-Random Sequence of Bits for Scan-Based BIST", Proc. of IEEE International Test Conference, pp. 167-175, 1996.

• N.A. Touba and E.J. McCluskey, "Test Point Insertion Based on Path Tracing", Proc. of IEEE VLSI Test Symposium, pp. 2-8, 1996.

• N.A. Touba and E.J. McCluskey, "Applying Two-Pattern Tests Using Scan-Mapping", Proc. of IEEE VLSI Test Symposium, pp. 393-397, 1996.

  1995

• N.A. Touba and E.J. McCluskey, "Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST", Proc. of IEEE International Test Conference, pp. 674-682, 1995.

• N.A. Touba and E.J. McCluskey, "Transformed Pseudo-Random Patterns for BIST", Proc. of IEEE VLSI Test Symposium, pp. 410-416, 1995.

  1994

• N.A. Touba and E.J. McCluskey, "Logic Synthesis Techniques for Reduced Area Implementation of Multilevel Circuits with Concurrent Error Detection", Proc. of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 651-654, 1994.

• N.A. Touba and E.J. McCluskey, "Automated Synthesis of Random Pattern Testable Circuits", Proc. of IEEE International Test Conference, pp. 174-183, 1994.

• S.Ghosh, S.Basu, and N.A. Touba, "Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering", Technical Report UT-CERC-TR-NAT02-1, Computer Engineering Research Center, University of Texas-Austin, 2002.

• N.A. Touba and E.J. McCluskey, "Ph.D. Thesis - Synthesis Techniques for Pseudo-Random Built-In Self-Test", Technical Report 96-4, Center for Reliable Computing, Stanford University, Aug. 1996.

• N.A. Touba and E.J. McCluskey, "Test Point Insertion for Non-Feedback Bridging Faults", Technical Report 96-3, Center for Reliable Computing, Stanford University, Aug. 1996.

• N.A. Touba and E.J. McCluskey, "Transformed Pseudo-Random Patterns for BIST", Technical Report 94-10, Center for Reliable Computing, Stanford University, Oct. 1994.

• N.A. Touba and E.J. McCluskey, "Logic Synthesis for Concurrent Error Detection", Technical Report 93-6, Center for Reliable Computing, Stanford University, Nov. 1993.

• R. Pan, N.A. Touba, and E.J. McCluskey, "The Effect of Fault Dropping on Fault Simulation Time", Technical Report 93-5, Center for Reliable Computing, Stanford University, Nov. 1993.

• N.A. Touba, "Reducing Synchronization in Concurrent Processes", Technical Report 92-3, Center for Reliable Computing, Stanford University, Feb. 1992.