;This example was developed in class March 24
;Purpose: 1 ms periodic interrupt
;         debugging with logic analyzer

PTT      equ $0240  ; Port T I/O Register
DDRT     equ $0242  ; Port T Data Direction Register
TC0      equ $0050  ; Timer Input Capture/Output Compare Register 0
TCNT     equ $0044  ; Timer Count Register
TFLG1    equ $004E  ; Main Timer Interrupt Flag 1
TIE      equ $004C  ; Timer Interrupt Enable Register
TIOS     equ $0040  ; Timer Input Capture/Output Compare Select
TSCR1    equ $0046  ; Timer System Control Register1
TSCR2    equ $004D  ; Timer System Control Register 2

      org  $0800
Count rmb  1     ;number of interrupts
      org  $4000
main  lds  #$4000
      movb #$80,TSCR1 ;turn on clock
      movb #3,TSCR2   ;divide by 8
      bset TIOS,#1    ;output compare channel 0
      bset TIE,#1     ;arm channel 0
      ldd  TCNT
      addd #1000
      std  TC0     ;set time for first interrupt
      bset DDRT,#3 ;debugging monitors
      clr  Count
      cli          ;enable interrupts
loop
      bset PTT,#2
      bclr PTT,#2  ;PT1 toggles
      bra  loop
      org *
TC0isr
;C0F set when TC0==TCNT, every 1ms
      bset PTT,#1  ;debugging monitor
      ldaa #1
      staa TFLG1   ;ack, make it zero
      ldd  TC0
      addd #1000
      std  TC0
;--    ldaa PTT
;--    eora #1  ;PT0
;--    staa PTT
      inc  Count
      bclr PTT,#1 ;PT0
      rti

      org  $FFEE
      fdb  TC0isr ;channel 0 vector
      org $FFFE
      fdb main