EE345M Microcomputer Interfacing Lab Spring 2001
Class: ENS115 Monday, Wednesday 9 to 9:50am
Office Hours: Office Hours Mon. 10-11am, Wed. 12-1pm, Fri. 9 am to 11am
Instructor: Jonathan W. Valvano, ENS617A, 471-5141, Lab ENS619/621 (1-1216)
email valvano@uts.cc.utexas.edu
fax 471-0616
Web page http://www.ece.utexas.edu/~valvano
Unique Numbers: 14610 Tue 9-12, 14615 Tue 7-10, 14620 Thur 7-10
EE345L and EE345M TAs:
Hyunjin Shin <hjshin@ece.utexas.edu> Tue 9am-12noon, Tue
7-10 pm
Anand Rajan <arajan@ece.utexas.edu> Wed 12-3pm, Thur 7-10pm
Preetha Parthasarathy <preetha@mail.utexas.edu> Wed 3-5:30pm,
Thu 3-6pm
Chia-ling Wei <clwei@mail.utexas.edu> Tue 9am-12noon,
Wed 7-10pm
Handout: Motorola CPU12 Reference Manual,
The 6812 Technical Summary is available as a pdf file on the lab
network and on the CD
Text: Embedded Microcomputer Systems, Brooks-Cole 2000, by J.W. Valvano
IEEE Parts: any TTL Data Book includes either LSTTL or HC parts
1 prototype board per student (2 per group)
Lab supplies: resistors, 3.5 inch floppy disks, lock for 2nd floor locker
HKN: Spring 2001 EE345M Laboratory Manual by J.W. Valvano
Other references: For programming in C and op amps, see the EE360C and EE338K
texts
Also see Kelly/Pohl, A Book on C, Benjamin Cumming Publishing
Prerequisites: EE345L or EE345S, EE338K, and EE155. There will be no re-tests,
make-ups, or incompletes.
Specific Objectives of EE345M
Review of 6812 architecture, and C programming
Synchronization methods
Gadfly, interrupt, DMA, periodic polling, priority interrupts
Real time operating systems
Foreground and background thread scheduling
Synchronization using spinlock and blocking semaphores
Interthread communication, networks
Digital Device Interfaces
Diodes, transistors, DC motors, servos, stepper motors, relays,
solenoids,
Optical sensors and optical isolation
Time Domain Interfaces
Input capture/output compare, frequency, period and pulse width
measurements,
Pulse-width modulation
Data Acquisition Systems
Op amp amplifiers, analog filters, DAC, ADC
Thread scheduling, digital filters
Control systems
Open loop and closed loop, Linear and Nonlinear,
Bang-bang, incremental, PID, Fuzzy Logic Control
Review of Microcomputer Bus Interfaces
Timing equations, timing diagrams,
Address translation and extended mode
Attendance: Students are expected to attend lectures. The book covers more
information than the class and we will use lectures to map our
way through the book. If you miss class you may find it difficult
to catch up.
Grading: 40% Laboratory
15% In class Quiz1, Wednesday, February 28, 9:00 am to
9:50 am, in regular class room
15% In class Quiz2, Wednesday, April 4, 9:00 am to 9:50
am, in regular class room
30% Final, Saturday, May 12, 2-5pm, regularly scheduled
Your grade will be assigned on the usual 60, 70, 80, 90 basis.
An average above 70 is required to receive a credit (CR/NR).
Lab Partners: All labs should be performed with a partner. The lab partnership
must be registered with the TA (a simple hand written note signed
by both students will suffice) at least a week before the assignment
is due. Once registered, the partnership will continue. A partnership
can be dissolved only after discussion with the TA. Both partners
must be present during the demonstration. It is expected that
both partners will contribute to all aspects of each lab, and
both partners are expected to be present during the check out.
The point values are the same for all labs. The TA will sign your
software listing when you demonstrate your system. All parts of
the assignment must be demonstrated to a TA by the end of your
lab period the week shown in the column labeled "Demo/Report".
The report (hardware/software/data plots) are due one day after
the demonstration is due. Please consult with your TA for specific
due dates for your lab section.
EE345M Laboratories
13. Real time debugging (1 week)
14. Optical isolation, pulse width modulated squarewave generation,
motor interface (1 week)
15. Period measurement of a DC motor tachometer (1 week)
16b. IR Remote Control (TExaS simulator) (1 week)
17b. Real time operating system (2 weeks) (handout, not in lab
manual)
11b. BSC Network (1 week) (handout, not in lab manual)
21. Digital to analog conversion, sine wave generation (1 week)
22. Temperature data acquisition, analog amp, analog filter, and
digital filter (2 weeks)
23 or 24 or 25. Embedded System (2 weeks)
23. PID or fuzzy logic motor control, pulse width modulation,
period measurement
24. Line tracking robot
25. Solid state secondary storage (handout, not in lab manual)
EE345M Laboratory Schedule (see your TA for the latest)
Week of
Quiz
Preparation
Demo/Report
Comments
1/22
none
none
none
Demonstration, Partners chosen
1/29
13
13
none
Get boards, bring lock
2/5
14
14
13
2/12
15
15
14
2/19
16b
16b
15
2/26
17b
17b
16b
3/5
none
none
none
Lab attendance required
3/19
11b
11b
17b
3/26
21
21
11b
4/2
22
22
21
4/9
none
none
none
4/16
23/24/25
23/24/25
22
4/23
none
none
none
Lab attendance required
4/30
none
none
23/24/25
Turn in equipment by 5/4
You have the option of proposing an alternative last lab involving
any topic introduced in EE345L or EE345M, forming groups of ranging
from 2 to 4 students. These groups may include students from other
lab sections. Please get your TA approval by 11/1, if you choose
to define your own last lab. Otherwise, we expect you to do Lab
23, 24 or 25 as a group of 2 as specified in the lab manual.
During the week of January 22, please go to your regularly scheduled
lab in ENS252C to hear a TA explain the lab grading policy. If
you miss your section, go to one of the other sessions. ImageCraft
Adapt812 boards will be passed out and lab partners will be selected
in your lab the week of January 22-26. The Lab 13 preparation
is due at the beginning of your lab the week of January 29-February
2. Preparation includes hardware wiring diagrams and syntax-free
assembly printouts. In other words, please type your software
into the PC before lab. The lab preparations (hardware diagrams
and syntax-free software source code printouts) are due at the
beginning of your lab period. Attendance in lab is required. All
software for lab, and tests must include comments. All hardware
must include R&C values specifying tolerance and type (e.g., 5%
carbon), and TTL chip numbers (be very specific e.g., 74LS00).
Pin numbers are required only for lab.
Students are encouraged to go to the last 2 hours of the other
lab periods (including when EE345L labs are scheduled), but the
first priority will be to the regular students. Because of the
lab quiz, the first hour of lab is restricted to the regular students.
CLEAR OUT BY 15 minutes before the start of lab. At the end of
the semester please verify with the checkout counter that your
record is clear. All reports must be given to the TA by Friday
May 4, 12 noon..
Date
Chapter
Topic
1/17
1, 2
EE345L review, 6812 introduction, device drivers
1/22
2, 4, 7
Lab environment, 6812 debugging techniques, SCI interrupts on
the 6812
1/24
8, 6
Transistor interfaces, optical isolation, PWM
1/29
6
Periodic output compare interrupts, PWM
1/31
6
Input capture, simple period and pulse width measurement
2/5
5
Threads, TCB, switching
2/7
5
Spinlock semaphores
2/12
5
Blocking semaphores and thread communication
2/14
14
networks
2/19
5,14
Simple memory manager and thread synchronization
2/21
9
Timing diagrams, 6812 data bus timing, ROM interface
2/26
1,2,4,6,7
Quiz 1 in class, open book, covering material in Labs 13,14,15,16
2/28
9
6812 RAM interface, extended memory
3/5
11
DAC, Signal generation
3/7
11, 12
Analog Circuits, amplifiers filters
3/19
12
ADC, data acquisition systems
3/21
12
Data acquisition systems
3/26
15
Digital filters
3/28
5, 15
Real time signal processing
4/2
13
Control systems
4/4
13
PID control systems
4/9
13
Fuzzy Logic Control Systems
4/11
8
Push/pull motor interface
4/16
Industrial guest speaker
4/18
5,11,12
Quiz 2 in class, open book, covering material in Labs 17b,11b,21,22
4/23
9
extended memory, address translation, solid state disk
4/25
10
High speed interfaces
4/30
10
DMA on the MC68HC708XL36
5/2
all
Review, course evaluation
5/4
All Lab notebooks are due to the TA at 12 noon
5/4
Turn in Lab Equipment so that Mona wont bar your registration
5/12
Final exam, Sat, May 12, 2-5pm, Room regularly scheduled
Legal Stuff: Drop date is January 31. After this date, I will sign a drop only
if the Dean approves it. Your current grade status must be a "C"
or better for you to receive a "Q". Course evaluation is conducted
on the last class day in accordance with the Measurement and Evaluation
Center form. The final exam is at the time and place stated in
the course schedule. The University of Texas at Austin provides
upon request appropriate academic adjustments for qualified students
with disabilities. For more information, contact the Office of
the Dean of Students with Disabilities at 471-6259, 471-4241 TDD.
Cheating: Cheating is very uncivilized behavior and is to be avoided at
all cost. You are allowed to talk to your classmates about the
lab assignments, but you are NOT allowed to look at each others written work. Oral discussion about an assignment is encouraged and is not considered to be cheating. Copying of any part of a program is
cheating without explicit reference to its source. If we find
two programs that are copied, there will be a substantial penalty
to both students, e.g., failure in the course. Students who cheat
on tests or in lab will fail. Prosecution of cases is very traumatic
to both the student and instructor. PLEASE DO YOUR OWN WORK. Policies concerning the use of other peoples software in this
class:
I strongly encourage you to study existing software.
All applications and libraries must be legally obtained. E.g.,
You may use libraries that came when you bought a compiler.
You may use software obtained from a BBS or on the WWW.
You may copy and paste from the existing source code.
You may use any existing source code that is clearly referenced
and categorized:
original: completely written by you,
derived: fundamental approach is copied but it is your implementation,
modified: source code significantly edited to serve your purpose,
copied: source code includes minor modifications.
Places to buy prototyping boards and other parts
In Austin
AlTex Electronics
832-9131
Tinkertronics
719-3560
Howard Electronics
837-2525
Mail Order
BG Micro, Dallas
1-800-276-2206
www.bgmicro.com
All Electronics, Los Angeles
1-800-826-5432
www.allelectronics.com
Marlin P. Jones
1-800-652-6733
www.mpja.com
TechAmerica, Fort Worth
1-800-877-0072
Hosfelt, Steubenville, OH
1-888-264-6464, 1-800-524-6464
Jameco, Belmont CA
1-800-831-4242
www.jameco.com
STUDY GUIDE Quiz 1
Lab Important Topics
13. SCI interrupts, RS232 drivers, software device driver, real
time debugging
14. Optical isolation, pulse width modulation, transistor interfaces,
back EMF, MOSFETs
15. Period measurement, sine wave to square wave
16b. IR detector interface, input capture measurements of pulse
width, output compare interrupts
Chapter Topic
1.5, 2, 4 6812 architecture and assembly language,
interpreting output of the C compiler (parameters, locals
globals)
4 fifos, statically allocated linked lists, dynamically allocated
linked lists,
interrupts, latency, real time interrupts, periodic polling,
critical sections
3, 4 Choosing between real time, gadfly, interrupts, periodic
polling, DMA
6 Input capture, period measurement, pulse width measurement
6 Output compare, pulse-width modulation, frequency measurement
8.4, 8.5 6N139 isolation, solenoids, DC motors, back EMF
Guarantees
Interrupts: data structures, latency, debugging
Input capture or output compare: period or pulse width
measurement
STUDY GUIDE Quiz 2 (Quiz 1 stuff plus the following)
Lab Important Topics
17. Real time OS, semaphores, critical sections, synchronization,
communication
11b. Networks, communication, synchronization
21. DAC interface, DAC signal generation
22. 6812 ADC, analog amplifiers, analog filters, digital filters,
fixed point numbers, resistor bridge, op amps
Chapter Topic
9 Address decoding, timing syntax, synchronous, partially asynchronous,
fully asynchronous, general approach to interfacing,
interface of RAM and ROM to a 6812 in expanded narrow
mode,
interface of a RAM and ROM to a 6812 in expanded wide
mode,
data bus drivers (no 16 bit, paged memory, 6811, DRAM,
parity check)
11, 12 Analog Circuits, amplifiers filters, ADC, DAC, data acquisition
systems
11.9, 15 Digital filters implementations, multiple access circular
queue
14 BSC network
BSC protocol, checksums, error detection, error recovery,
Guarantees
Interrupt software
Memory interface: timing analysis, diagrams, design, CS
initialization
Data acquisition systems
Analog circuits
STUDY GUIDE Final (Quiz 1 and Quiz 2 stuff plus the following)
Lab Important Topics
23/24 Control system, either PID or Fuzzy, periodic interrupts,
AC to TTL conversion, input capture measurement of period, discrete
derivative
Chapter Topic
9 Address translation, paged memory
10 DMA concepts, single vs. dual cycle, block (burst) vs. cycle
steal, software synchronization, bandwidth, latency, address increment,
block size, autoinitialization (reloads parameters and loops continuously)
13 Control Systems, open loop, closed loop, PID implementations,
Fuzzy Logic design and implementation
Guarantees
Control system implementation
Multiple source interrupts with synchronization
Memory interface: timing analysis, diagrams, design, CS
initialization
Analog circuits
Input capture or output compare: measurement or signal
generation
Curious about my research? See
http://www.ece.utexas.edu/~valvano/research